Data gating using scan enable pin
An Integrated Circuit (IC) includes a storage element and control circuitry. The control circuitry is configured to select, responsively to a scan-enable control, between a functional-data input and a scan-data input to serve as an input to the storage element, to selectively disable toggling of an output of the storage element, responsively to a clock-enable control, by gating a clock signal provided to the storage element, and, while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, to select the input of the storage element to be the scan-data input.
1. An Integrated Circuit (IC), comprising:
a storage element having an input and an output; and control circuitry, configured to:
receive a clock-enable control; and
while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, prevent an input of the storage element from toggling, without adding latency to a functional-data input of the storage element, by setting the input to a constant logic state.
2. The IC according to claim 1 , wherein:
the storage element is a dual-latch Flip-Flop (FF) comprising a primary latch and a secondary latch,
in gating a clock signal provided to the storage element, the control circuit is configured to set the primary latch to a transparent mode, and
to prevent the input of the storage element from toggling, the control circuit is configured to set the input of the primary latch to the constant logic state.
3. The IC according to claim 1 , wherein the storage element comprises one or more latches, and wherein, in setting the input to the constant logic state, the control circuitry is configured to prevent any of the latches from toggling while the output is disabled from toggling, regardless of whether or not the functional-data input of the storage element is toggling.
4. The IC according to claim 1 , wherein, to set the input to the constant logic state, the control circuitry comprises a logic gate configured to set the storage element to a scan mode in response to the clock-enable control disabling a clock signal provided to the storage element.
5. The IC according to claim 1 , wherein the control circuitry comprises a logic gate, which is configured to set the input of the storage element to the constant logic state in response to the clock-enable control disabling a clock signal provided to the storage element.
6. A method in an Integrated Circuit (IC) that includes at least a storage element having an input and an output, the method comprising:
receiving a clock-enable control; and
while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, preventing an input of the storage element from toggling, without adding latency to a functional-data input of the storage elements, by setting the input to a constant logic state.
7. The method according to claim 6 , wherein:
the storage element is a dual-latch Flip-Flop (FF) comprising a primary latch and a secondary latch,
gating a clock signal provided to the storage element comprises setting the primary latch to a transparent mode, and
preventing an input of the storage element from toggling comprises setting the input of the primary latch to the constant logic state.
8. The method according to claim 6 , wherein the storage element comprises one or more latches, and wherein setting the input to the constant logic state comprises preventing any of the latches from toggling while the output is disabled from toggling, regardless of whether or not the functional-data input of the storage element is toggling.
9. The method according to claim 6 , wherein setting the input of the storage element to the constant logic state comprises setting the storage element to a scan mode using a logic gate, in response to the clock-enable control disabling a clock signal provided to the storage element.
10. The method according to claim 6 , wherein setting the input of the storage element to the constant logic state is performed using a logic gate, in response to the clock-enable control disabling a clock signal provided to the storage element.
11. An apparatus comprising a processor that comprises (i) fetch circuitry configured to fetch instructions and (ii) execute circuitry configured to execute instructions, wherein one or both of the fetch circuitry and the execute circuitry comprise:
a storage element having an input and an output; and
control circuitry, configured to:
receive a clock-enable control; and
while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, prevent an input of the storage element from toggling, without adding latency to a functional-data input of the storage element, by setting the input to a constant logic state.
12. The apparatus according to claim 11 , further comprising a display device and one or more input devices.
13. The apparatus according to claim 11 , wherein:
the storage element is a dual-latch Flip-Flop (FF) comprising a primary latch and a secondary latch,
in gating a clock signal provided to the storage element, the control circuit is configured to set the primary latch to a transparent mode, and
to prevent the input of the storage element from toggling, the control circuit is configured to set the input of the primary latch to the constant logic state.
14. The apparatus according to claim 11 , wherein the storage element comprises one or more latches, and wherein, in setting the input to the constant logic state, the control circuitry is configured to prevent any of the latches from toggling while the output is disabled from toggling, regardless of whether or not the functional-data input is toggling.
15. The apparatus according to claim 11 , wherein, to set the input to the constant logic state, the control circuitry comprises a logic gate configured to set the storage element to a scan mode in response to the clock-enable control disabling a clock signal provided to the storage element.
16. The apparatus according to claim 11 , wherein the control circuitry comprises a logic gate, which is configured to set the input of the storage element to the constant logic state in response to the clock-enable control disabling a clock signal provided to the storage element.