Data storage device and non-volatile memory control method
A technique for accurate communication between a non-volatile memory and its controller. The controller accesses a storage area of the non-volatile memory through data lines, wherein the controller transmits a command through the data lines to access the storage area of the non-volatile memory. The command is further returned from the non-volatile memory to the controller through the data lines for comparison, to determine whether the command is correctly received by the non-volatile memory.
1. A data storage device, comprising:
a non-volatile memory; and
a controller, coupled to the non-volatile memory and configured to control the non-volatile memory as requested by a host,
wherein:
the controller accesses a storage area of the non-volatile memory through data lines;
the controller transmits a command through the data lines to access the storage area of the non-volatile memory; and
the command is further returned from the non-volatile memory to the controller through the data lines for comparison between the returned command and the originally transmitted command, to determine whether the command is correctly received by the non-volatile memory based on comparison of command contents.
2. The data storage device as claimed in claim 1 , wherein:
in response to a write-enable signal, the non-volatile memory receives the command from the data lines as indicated by a command latch-enable signal; and
in response to a read-enable signal, the controller receives the returned command from the data lines as indicated by the command latch-enable signal.
3. The data storage device as claimed in claim 2 , wherein:
when the returned command is different from the command that the controller originally transmitted to the non-volatile memory, the controller resends the command to the non-volatile memory.
4. The data storage device as claimed in claim 3 , wherein:
the storage area is activated by a chip-enable signal;
in response to enablement of the chip enable signal, the non-volatile memory performs a recording process based on the write-enable signal, to record contents that are received from the data lines as indicated by the command latch-enable signal; and
prior to the chip-enable signal being disabled, the non-volatile memory ends the recording process and controls the read-enable signal to perform a return process, to return the recorded contents to the controller through the data lines as indicated by the command latch-enable signal.
5. The data storage device as claimed in claim 4 , wherein:
in the non-volatile memory, the recording process and the return process are performed in a first-in first-out manner.
6. The data storage device as claimed in claim 3 , wherein:
the controller further transmits an address through the data lines to access the storage area of the non-volatile memory; and
the address is further returned from the non-volatile memory to the controller through the data lines for comparison, to determine whether the address is correctly received by the non-volatile memory.
7. The data storage device as claimed in claim 6 , wherein:
in response to the write-enable signal, the non-volatile memory receives the address from the data lines as indicated by an address latch-enable signal; and
in response to the read-enable signal, the controller receives a comparison address returned from the data lines as indicated by the address latch-enable signal.
8. The data storage device as claimed in claim 7 , wherein:
when the comparison address is different from the address that the controller originally transmitted to the non-volatile memory, the controller resends the address to the non-volatile memory.
9. The data storage device as claimed in claim 8 , wherein:
the storage area is activated by a chip-enable signal;
in response to enablement of the chip enable signal, the non-volatile memory performs a recording process based on the write-enable signal, to record contents that are received from the data lines as indicated by the address latch-enable signal and the command latch-enable signal; and
prior to the chip-enable signal being disabled, the non-volatile memory ends the recording process and controls the read-enable signal to perform a return process, to return the recorded contents to the controller through the data lines as indicated by the address latch-enable signal and the command latch-enable signal.
10. The data storage device as claimed in claim 9 , wherein:
in the non-volatile memory, the recording process and the return process are performed in a first-in first-out manner.
11. A non-volatile memory control method, comprising:
operating a controller to access a storage area of a non-volatile memory through data lines, wherein the controller transmits a command through the data lines to access the storage area of the non-volatile memory; and
returning the command from the non-volatile memory to the controller through the data lines for comparison between the returned command and the originally transmitted command, to determine whether the command is correctly received by the non-volatile memory based on comparison of command contents.
12. The non-volatile memory control method as claimed in claim 11 , wherein:
in response to a write-enable signal, the non-volatile memory receives the command from the data lines as indicated by a command latch-enable signal; and
in response to a read-enable signal, the controller receives the returned command from the data lines as indicated by the command latch-enable signal.
13. The non-volatile memory control method as claimed in claim 12 , wherein:
when the returned command is different from the command that the controller originally transmitted to the non-volatile memory, the controller resends the command to the non-volatile memory.
14. The non-volatile memory control method as claimed in claim 13 , wherein:
the storage area is activated by a chip-enable signal;
in response to enablement of the chip enable signal, the non-volatile memory performs a recording process based on the write-enable signal, to record contents that are received from the data lines as indicated by the command latch-enable signal; and
prior to the chip-enable signal being disabled, the non-volatile memory ends the recording process and controls the read-enable signal to perform a return process, to return the recorded contents to the controller through the data lines as indicated by the command latch-enable signal.
15. The non-volatile memory control method as claimed in claim 14 , wherein:
in the non-volatile memory, the recording process and the return process are performed in a first-in, first-out manner.
16. The non-volatile memory control method as claimed in claim 13 , wherein:
the controller further transmits an address through the data lines to access the storage area of the non-volatile memory; and
the address is further returned from the non-volatile memory to the controller through the data lines for comparison, to determine whether the address is correctly received by the non-volatile memory.
17. The non-volatile memory control method as claimed in claim 16 , wherein:
in response to the write-enable signal, the non-volatile memory receives the address from the data lines as indicated by an address latch-enable signal; and
in response to the read-enable signal, the controller receives a comparison address returned from the data lines as indicated by the address latch-enable signal.
18. The non-volatile memory control method as claimed in claim 17 , wherein:
when the comparison address is different from the address that the controller originally transmitted to the non-volatile memory, the controller resends the address to the non-volatile memory.
19. The non-volatile memory control method as claimed in claim 18 , wherein:
the storage area is activated by a chip-enable signal;
in response to enablement of the chip enable signal, the non-volatile memory performs a recording process based on the write-enable signal, to record contents that are received from the data lines as indicated by the address latch-enable signal and the command latch-enable signal; and
prior to the chip-enable signal being disabled, the non-volatile memory ends the recording process and controls the read-enable signal to perform a return process, to return the recorded address to the controller through the data lines as indicated by the address latch-enable signal and the command latch-enable signal.
20. The non-volatile memory control method as claimed in claim 19 , wherein:
in the non-volatile memory, the recording process and the return process are performed in a first-in first-out manner.