IP Library Granted Patent US 12,293,430
Granted Patent B2
US 12,293,430 · App. 17/356,043 · Granted May 6, 2025

Typed unordered access view overloading on pixel pipeline

Inventors: Jay Jardosh (Folsom, CA); Prasoonkumar Surti (Folsom, CA); Abhishek R. Appu (El Dorado Hills, CA)
Assignee: Intel Corporation
G06T1/20G06T1/60
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Quick Facts
Patent No.
US 12,293,430
App. No.
17/356,043
Granted
May 6, 2025
Kind
B2
Abstract

Methods, systems and apparatuses provide for graphics processor technology that routes untyped unordered access view (UAV) messages to a next level memory cache, routes typed UAV messages and render target messages to a pixel pipeline, and processes, via the pixel pipeline, the typed UAV messages. The technology can also provide for the pixel pipeline to perform a format conversion of one or more pixels associated with a typed UAV message based on a surface format of a UAV resource, calculate a memory address for each pixel associated with the typed UAV message, and collect a plurality of fragments from processed typed UAV messages.

Claims (54)

1. A computing system comprising:

a network controller; and

a graphics processor coupled to the network controller, wherein the graphics processor includes logic coupled to one or more substrates, the logic comprising:

a pixel pipeline to process typed unordered access view (UAV) messages; and

a message router to:

route untyped UAV messages to a next level memory cache; and

route typed UAV messages and render target messages to the pixel pipeline.

2. The computing system of claim 1 , wherein to process the typed UAV messages, the pixel pipeline is to:

perform a format conversion of one or more pixels associated with a typed UAV message based on a surface format of a UAV resource;

calculate a memory address for each pixel associated with the typed UAV message; and

collect a plurality of fragments from processed typed UAV messages.

3. The computing system of claim 2 , wherein to perform a format conversion of one or more pixels associated with a typed UAV message comprises to convert a 32 bit per channel format to one of an 8 bit per channel format or a 16 bit per channel format.

4. The computing system of claim 2 , wherein to calculate a memory address for each pixel associated with the typed UAV message comprises using location coordinates and surface properties associated with each respective pixel.

5. The computing system of claim 2 , wherein the plurality of fragments from processed typed UAV messages are collected based on an address boundary associated with each of the fragments.

6. The computing system of claim 5 , wherein the plurality of fragments are collected so long as the address of each fragment falls within a threshold address range, and wherein the pixel pipeline is further to route the collected plurality of fragments to the next level memory cache once a next fragment falls outside of the threshold address range.

7. A semiconductor apparatus comprising:

one or more substrates; and

logic coupled to the one or more substrates, the logic implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic comprising:

a pixel pipeline to process typed unordered access view (UAV) messages; and

a message router to:

route untyped UAV messages to a next level memory cache; and

route typed UAV messages and render target messages to the pixel pipeline.

8. The apparatus of claim 7 , wherein to process the typed UAV messages, the pixel pipeline is to:

perform a format conversion of one or more pixels associated with a typed UAV message based on a surface format of a UAV resource;

calculate a memory address for each pixel associated with the typed UAV message; and

collect a plurality of fragments from processed typed UAV messages.

9. The apparatus of claim 8 , wherein to perform a format conversion of one or more pixels associated with a typed UAV message comprises to convert a 32 bit per channel format to one of an 8 bit per channel format or a 16 bit per channel format.

10. The apparatus of claim 8 , wherein to calculate a memory address for each pixel associated with the typed UAV message comprises using location coordinates and surface properties associated with each respective pixel.

11. The apparatus of claim 8 , wherein the plurality of fragments from processed typed UAV messages are collected based on an address boundary associated with each of the fragments.

12. The apparatus of claim 11 , wherein the plurality of fragments are collected so long as the address of each fragment falls within a threshold address range, and wherein the pixel pipeline is further to route the collected plurality of fragments to the next level memory cache once a next fragment falls outside of the threshold address range.

13. At least one non-transitory computer readable storage medium comprising a set of instructions which, when executed by a graphics apparatus, cause the graphics apparatus to:

route untyped unordered access view (UAV) messages to a next level memory cache;

route typed UAV messages and render target messages to a pixel pipeline; and

process, by the pixel pipeline, the typed UAV messages.

14. The at least one non-transitory computer readable storage medium of claim 13 , wherein to process the typed UAV messages, the pixel pipeline is to:

perform a format conversion of one or more pixels associated with a typed UAV message based on a surface format of a UAV resource;

calculate a memory address for each pixel associated with the typed UAV message; and

collect a plurality of fragments from processed typed UAV messages.

15. The at least one non-transitory computer readable storage medium of claim 14 , wherein to perform a format conversion of one or more pixels associated with a typed UAV message comprises to convert a 32 bit per channel format to one of an 8 bit per channel format or a 16 bit per channel format.

16. The at least one non-transitory computer readable storage medium of claim 14 , wherein to calculate a memory address for each pixel associated with the typed UAV message comprises using location coordinates and surface properties associated with each respective pixel.

17. The at least one non-transitory computer readable storage medium of claim 14 , wherein the plurality of fragments from processed typed UAV messages are collected based on an address boundary associated with each of the fragments.

18. The at least one non-transitory computer readable storage medium of claim 17 , wherein the plurality of fragments are collected so long as the address of each fragment falls within a threshold address range, and wherein the instructions, when executed, further cause the graphics apparatus to route the collected plurality of fragments to the next level memory cache once a next fragment falls outside of the threshold address range.

19. A method comprising:

routing untyped unordered access view (UAV) messages to a next level memory cache;

routing typed UAV messages and render target messages to a pixel pipeline; and

processing, by the pixel pipeline, the typed UAV messages.

20. The method of claim 19 , wherein processing the typed UAV messages comprises:

performing a format conversion of one or more pixels associated with a typed UAV message based on a surface format of a UAV resource;

calculating a memory address for each pixel associated with the typed UAV message; and

collecting a plurality of fragments from processed typed UAV messages.

21. The method of claim 20 , wherein performing a format conversion of one or more pixels associated with a typed UAV message comprises converting a 32 bit per channel format to one of an 8 bit per channel format or a 16 bit per channel format.

22. The method of claim 20 , wherein calculating a memory address for each pixel associated with the typed UAV message comprises using location coordinates and surface properties associated with each respective pixel.

23. The method of claim 20 , wherein the plurality of fragments from processed typed UAV messages are collected based on an address boundary associated with each of the fragments.

24. The method of claim 23 , wherein the plurality of fragments are collected so long as the address of each fragment falls within a threshold address range, and further comprising routing the collected plurality of fragments to the next level memory cache once a next fragment falls outside of the threshold address range.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2022
From: JARDOSH, JAY; SURTI, PRASOONKUMAR; APPU, ABHISHEK R.
To: INTEL CORPORATION
Reel/Frame 059224/0008 →
Continuity (1)
Related Publication 20220414813A1 · Dec 29, 2022
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