IP Library › Granted Patent US 12,295,135
Granted Patent B2
US 12,295,135 · App. 17/656,769 · Granted May 6, 2025

Memory device, and semiconductor structure and forming method thereof

Inventor: Shih-Hung Lee (Hefei, CN)
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
H10B12/053G11C11/161H10B12/34H10B61/22H10N50/01H10N50/85
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,295,135
App. No.
17/656,769
Granted
May 6, 2025
Kind
B2
Abstract

The present disclosure relates to the technical field of semiconductors, and provides a memory device, and a semiconductor structure and a forming method thereof. The forming method includes: providing a substrate, where the substrate includes a source region and a drain region spaced apart from each other, and a gate trench located between the source region and the drain region; forming, in sequence on an inner wall of the gate trench, a gate oxide layer, an interface layer, and a conductive layer that fills the gate trench; and etching back the side of the interface layer away from the bottom of the gate trench by using a wet etching process, such that a top height of the interface layer is lower than a top height of the conductive layer.

Claims (22)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a source region and a drain region spaced apart from each other, and a gate trench located between the source region and the drain region;

forming, in sequence on an inner wall of the gate trench, a gate oxide layer, an interface layer, and a conductive layer that fills the gate trench; a thickness of a side of the interface layer away from a bottom of the gate trench being greater than a thickness of a side of the interface layer close to the bottom of the gate trench; and

etching back the side of the interface layer away from the bottom of the gate trench by using a wet etching process, such that a top height of the interface layer is lower than a top height of the conductive layer;

wherein the forming, in sequence on an inner wall of the gate trench, a gate oxide layer, an interface layer, and a conductive layer that fills the gate trench; a thickness of a side of the interface layer away from a bottom of the gate trench being greater than a thickness of a side of the interface layer close to the bottom of the gate trench comprises:

forming, in sequence on the inner wall of the gate trench, a fittedly attached gate oxide layer and a fittedly attached first interface layer, and a first conductive material that fills the gate trench;

etching the first conductive material by using a dry etching process, to expose a part of the first interface layer located on a side wall of the gate trench;

forming a second interface layer on a surface of the first interface layer located on the side wall of the gate trench, wherein the first interface layer and the second interface layer constitute the interface layer; and

depositing a second conductive material on a surface of the first conductive material away from the gate oxide layer, and wrapping the second interface layer around a periphery of the second conductive material, wherein a side of the second interface layer close to the bottom of the gate trench may be in contact with a remaining surface of the first conductive material away from the gate oxide layer.

2. The method of forming a semiconductor structure according to claim 1 , wherein the etching back the side of the interface layer away from the bottom of the gate trench by using a wet etching process, such that a top height of the interface layer is lower than a top height of the conductive layer comprises:

etching the interface layer by using a selective wet etching process, such that the top height of the interface layer is lower than the top height of the conductive layer.

3. The method of forming a semiconductor structure according to claim 2 , wherein an etching selectivity of the interface layer to the conductive layer is 5 to 40.

4. The method of forming a semiconductor structure according to claim 1 , wherein a depth of the gate trench is 100 nm to 300 nm, and a width of the gate trench is 10 nm to 50 nm.

5. The method of forming a semiconductor structure according to claim 4 , wherein an etching depth of the first conductive material is 5 nm to 70 nm, and an etching back depth of the interface layer is 5 nm to 50 nm.

6. The method of forming a semiconductor structure according to claim 1 , wherein the forming a second interface layer on a surface of the first interface layer located on the side wall of the gate trench comprises:

depositing an interface material on a surface of a structure constituted by the first conductive material, the first interface layer, and the gate oxide layer; and

removing the interface material located on a region other than the side wall of the gate trench by using the dry etching process to form the second interface layer.

7. The method of forming a semiconductor structure according to claim 1 , wherein the depositing a second conductive material on a surface of the first conductive material away from the gate oxide layer, and wrapping the second interface layer around a periphery of the second conductive material comprises:

depositing the second conductive material on a side of the first conductive material away from the gate oxide layer, wherein the second conductive material covers the second interface layer; and

removing the second conductive material overflowing the gate trench by using the dry etching process, wherein the first conductive material and the second conductive material constitute the conductive layer.

8. The method of forming a semiconductor structure according to claim 1 , wherein a material of the first conductive material is the same as a material of the second conductive material.

9. The method of forming a semiconductor structure according to claim 1 , wherein a thickness of the first interface layer is 0.5 nm to 2 nm, and a thickness of the second interface layer is 2 nm to 10 nm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2024
From: LEE, SHIH-HUNG
To: CHANGXIN MEMORY TECHNOLOGIES, INC.
Reel/Frame 067620/0418 →
Priority Claims (1)
CN 202110067276.1 · Jan 19, 2021 · national
Continuity (2)
Continuation PCTCN2021112022 · Aug 11, 2021
Related Publication 20220231028A1 · Jul 21, 2022
References Cited (25)
US 5241193A · Pfiester et al. · 1993 [cited by applicant]
US 8211775B1 · Ma et al. · 2012 [cited by applicant]
US 8420484B2 · Yoo · 2013 [cited by applicant]
US 8470702B2 · Yang · 2013 [cited by applicant]
US 9224619B2 · Yi et al. · 2015 [cited by applicant]
US 10050038B2 · Lee et al. · 2018 [cited by applicant]
US 10790287B2 · Kang et al. · 2020 [cited by applicant]
US 20040235253A1 · Kim · 2004 [cited by examiner]
US 20060097314A1 · Uchiyama · 2006 [cited by examiner]
US 20070200178A1 · Yun et al. · 2007 [cited by applicant]
US 20080138952A1 · Cho et al. · 2008 [cited by applicant]
US 20080268588A1 · Anderson · 2008 [cited by examiner]
US 20100065926A1 · Yeh · 2010 [cited by examiner]
US 20150221742A1 · Yi · 2015 [cited by examiner]
US 20160172488A1 · Oh · 2016 [cited by examiner]
US 20170365608A1 · Lee · 2017 [cited by examiner]
US 20180097084A1 · Wang · 2018 [cited by examiner]
US 20190229198A1 · Huang · 2019 [cited by examiner]
US 20190259839A1 · Ryu · 2019 [cited by examiner]
CN 101789368A · 2010 [cited by applicant]
CN 105990137A · 2016 [cited by applicant]
CN 107527912A · 2017 [cited by applicant]
CN 108110005A · 2018 [cited by applicant]
International Search Report cited in PCT/CN2021/112022 mailed Nov. 19, 2021, 9 pages. [cited by applicant]
State Intellectual Property Office of the People's Republic of China, First Office Action and Search Report Issued in Application No. 202110067276.1, Jun. 13, 2024, 11 pages. [cited by applicant]