Foveated display
An electronic device such as a head-mounted device may have displays. The display may have regions of lower and higher resolution to reduce data bandwidth and power consumption for the display while preserving satisfactory image quality. Data lines may be shared by lower and higher resolution portions of a display or different portions of a display with different resolutions may be supplied with different numbers of data lines. Data line length may be varied in transition regions between lower resolution and higher resolution portions of a display to reduce visible discontinuities between the lower and higher resolution portions. The lower and higher resolution portions of the display may be dynamically adjusted using dynamically adjustable gate driver circuitry and dynamically adjustable data line driver circuitry.
1. A display, comprising:
an array of pixels having rows and columns;
a plurality of gate lines that is configured to provide gate signals to the rows;
a plurality of data lines that is configured to provide data signals to the columns;
gate line driver circuitry configured to supply the gate signals to the plurality of gate lines; and
data line driver circuitry configured to supply the data signals to the plurality of data lines, wherein the data line driver circuitry comprises:
column buffer circuitry with a plurality of operational amplifiers, wherein a subset of the plurality of operational amplifiers receives a first signal in a first resolution mode and wherein the subset of the plurality of operational amplifiers receives a second signal in a second resolution mode; and
a data line multiplexer that is configured to provide the data signals from the column buffer circuitry to the data lines.
2. The display defined in claim 1 , wherein the data line driver circuitry comprises digital-to-analog converter circuitry that converts digital image data into the data signals and wherein the data signals are analog data signals.
3. The display defined in claim 1 , wherein each operation amplifier is associated with a respective data line of the plurality of data lines.
4. The display defined in claim 3 , wherein, in the first resolution mode, the subset of the plurality of operational amplifiers is disabled.
5. The display defined in claim 4 , wherein, in the first resolution mode, each operational amplifier in an additional subset of the plurality of operation amplifiers drives a single data signal into multiple data lines.
6. The display defined in claim 3 , wherein, in the second resolution mode, the subset of the plurality of operational amplifiers is enabled.
7. The display defined in claim 1 , wherein the gate line driver circuitry comprises a shift register and gate line multiplexer circuitry that is configured to provide the gate signals from the shift register to the gate lines.
8. The display defined in claim 7 , wherein the gate line multiplexer circuitry comprises a plurality of gate line multiplexers that are controlled by a common mode control signal.
9. The display defined in claim 8 , wherein at least one of the gate line multiplexers is configurable to operate in at least a first gate line multiplexer mode in which each of the gate lines receives an independent gate line signal from the at least one gate line multiplexer and a second gate line multiplexer mode in which each adjacent pair of the gate lines is provided with a common gate line signal for that pair from the at least one gate line multiplexer.
10. The display defined in claim 1 , wherein the data line multiplexer has a plurality of switches each of which is coupled to a respective pair of operational amplifiers of the plurality of operational amplifiers in the column buffer circuitry and each of which is coupled to a respective pair of the data lines.
11. The display defined in claim 1 , wherein, in the second resolution mode, all of the plurality of operational amplifiers is enabled.
12. The display defined in claim 1 , wherein the first signal is different than the second signal and the first resolution mode is different than the second resolution mode.
13. A display, comprising:
an array of pixels having rows and columns;
a plurality of gate lines that is configured to provide gate signals to the rows;
a plurality of data lines that is configured to provide data signals to the columns;
gate line driver circuitry configured to supply the gate signals to the plurality of gate lines; and
data line driver circuitry configured to supply the data signals to the plurality of data lines, wherein the data line driver circuitry comprises:
column buffer circuitry; and
a data line multiplexer that is configured to provide the data signals from the column buffer circuitry to the data lines, wherein the data line multiplexer comprises a plurality of switches that selectively shorts adjacent data lines in the plurality of data lines in a first resolution mode and isolates the adjacent data lines in the plurality of data lines in a second resolution mode.
14. The display defined in claim 13 , wherein selectively shorting adjacent data lines in the plurality of data lines comprises providing the same data line signals to the adjacent data lines in the plurality of data lines.
15. The display defined in claim 13 , wherein the column buffer circuitry has a plurality of operational amplifiers, and wherein a subset of the plurality of operational amplifiers is selectively disabled when the plurality of switches selectively shorts the adjacent data lines in the plurality of data lines.