IP Library › Granted Patent US 12,300,538
Granted Patent B2
US 12,300,538 · App. 18/346,573 · Granted May 13, 2025

Fin field effect transistor (FinFET) device structure with protection layer and method for forming the same

Inventors: Chien-Yuan Chen (Taichung, TW); Chen-Ming Lee (Taoyuan, TW); Fu-Kai Yang (Hsinchu, TW); Mei-Yun Wang (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L21/76849H01L23/5226H01L23/53209H10D30/024H10D30/62H10D30/6219H01L21/76831H01L21/7684H01L21/76844
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Quick Facts
Patent No.
US 12,300,538
App. No.
18/346,573
Granted
May 13, 2025
Kind
B2
Abstract

A FinFET device structure is provided. The FinFET device structure includes a gate structure formed over a fin structure, and an S/D contact structure formed adjacent to the gate structure. The FinFET device structure includes a protection layer formed on the S/D contact structure, and an S/D conductive plug formed over the protection layer. The S/D conductive plug is electrically connected to the S/D contact structure by the protection layer.

Claims (40)

1. A fin field effect transistor (FinFET) device structure, comprising:

a gate structure formed over a fin structure;

an S/D contact structure formed adjacent to the gate structure;

a protection layer formed on the S/D contact structure; and

an S/D conductive plug formed over the protection layer, wherein the S/D conductive plug is electrically connected to the S/D contact structure by the protection layer.

2. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the S/D conductive plug comprises a barrier layer, and a bottom surface of the barrier layer is curved.

3. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the S/D conductive plug is surrounded by an insulating layer, and a sidewall surface of the insulating layer is aligned with a sidewall surface of the protection layer.

4. The fin field effect transistor (FinFET) device structure as claimed in claim 3 , wherein a sidewall surface of the protection layer extends beyond a sidewall surface of the insulating layer.

5. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , further comprising:

an etching stop layer formed over the protection layer, wherein a portion of the etching stop layer is in direct contact with the protection layer.

6. The fin field effect transistor (FinFET) device structure as claimed in claim 5 , wherein etching stop layer has a protruding portion which is directly on the protection layer.

7. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the S/D conductive plug comprises a U-shaped structure in direct contact with the protection layer.

8. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the protection layer has a curved top surface and a curved bottom surface.

9. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , further comprising:

an S/D structure below the S/D contact structure; and

a metal silicide layer formed over the S/D structure, wherein the metal silicide layer is between the S/D structure and the S/D contact structure.

10. A fin field effect transistor (FinFET) device structure, comprising:

a gate structure formed over a fin structure;

a dielectric layer formed over the gate structure;

an S/D contact structure formed adjacent to the gate structure and in the dielectric layer; and

a protection layer formed on the S/D contact structure, wherein the protection layer is a conductive layer, and an interface between the S/D contact structure and the protection layer is lower than a top surface of the dielectric layer.

11. The fin field effect transistor (FinFET) device structure as claimed in claim 10 , further comprising:

an S/D conductive plug formed over the protection layer, wherein the S/D conductive plug is electrically connected to the S/D contact structure by the protection layer.

12. The fin field effect transistor (FinFET) device structure as claimed in claim 11 , wherein the S/D conductive plug is surrounded by an insulating layer, and a sidewall surface of the insulating layer is aligned with a sidewall surface of the protection layer.

13. The fin field effect transistor (FinFET) device structure as claimed in claim 10 , wherein the S/D contact structure is surrounded by an insulating layer, and a bottom surface of the protection layer is lower than a top surface of the insulating layer.

14. The fin field effect transistor (FinFET) device structure as claimed in claim 10 , further comprising:

a barrier layer surrounding the S/D contact structure, wherein the protection layer is not formed on a top surface of the barrier layer.

15. The fin field effect transistor (FinFET) device structure as claimed in claim 10 , wherein the protection layer has a curved bottom surface.

16. A fin field effect transistor (FinFET) device structure, comprising:

a fin structure formed along a first direction over a substrate;

a gate structure formed over the fin structure along a second direction;

a dielectric layer formed over the gate structure;

an S/D contact structure formed adjacent to the gate structure along a third direction; and

a protection layer formed on the S/D contact structure, wherein a top surface of the protection layer is higher than a top surface of the dielectric layer, and a bottom surface of the protection layer is lower than the top surface of the dielectric layer.

17. The fin field effect transistor (FinFET) device structure as claimed in claim 16 , wherein the S/D contact structure is surrounded by an insulating layer, and the bottom surface of the protection layer is lower than a top surface of the insulating layer.

18. The fin field effect transistor (FinFET) device structure as claimed in claim 16 , wherein the protection layer is made of a conductive material.

19. The fin field effect transistor (FinFET) device structure as claimed in claim 16 , further comprising:

an S/D conductive plug formed over the protection layer, wherein the S/D conductive plug comprises a barrier layer, and the barrier layer has a curved bottom surface in direct contact with the protection layer.

20. The fin field effect transistor (FinFET) device structure as claimed in claim 16 , further comprising:

a barrier layer surrounding the S/D contact structure, wherein the protection layer is not formed on the barrier layer.

Continuity (4)
Continuation 17120827 · Dec 14, 2020
Division 16124527 · Sep 7, 2018
Provisional Application 62586361 · Nov 15, 2017
Related Publication 20230369110A1 · Nov 16, 2023
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