On-die termination
Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.
1. A memory module comprising:
a module connector having a data contact to communicate write data and read data and control contacts to communicate module commands and addresses, a first termination-control signal, and a second termination-control signal, the data contact exhibiting a termination impedance;
a first rank of memory devices, each memory device in the first rank of memory devices including:
a first termination circuit coupled to the data contact to apply a first controlled impedance; and
first control logic coupled to the control contacts and the first termination circuit, the first control logic to control the first termination circuit;
the first control logic to select the first controlled impedance responsive to a first logical combination of the first termination-control signal and the second termination control signal; and
a second rank of memory devices, each memory device in the second rank of memory devices including:
a second termination circuit coupled to the data contact to apply a second controlled impedance; and
second control logic coupled to the control contacts and the second termination circuit, the second control logic to control the second termination circuit;
the second control logic to select the second controlled impedance responsive to a second logical combination of the first termination-control signal and the second termination control signal.
2. The memory module of claim 1 , wherein the termination impedance of the data contact is a function of the first controlled impedance and the second controlled impedance.
3. The memory module of claim 2 , wherein the first controlled impedance and the second controlled impedance are adjustable.
4. The memory module of claim 3 , wherein each of the memory devices in the first rank of memory devices includes a register to a first value for the first controlled impedance and a second value for the second controlled impedance.
5. The memory module of claim 4 , wherein the values select the first controlled impedance from among a high impedance, a first termination impedance, and a second termination impedance.
6. The memory module of claim 5 , wherein the high impedance consists essentially of an open circuit.
7. The memory module of claim 1 , wherein the first controlled impedance differs from the second controlled impedance responsive to a shared combination of the first termination-control signal and the second termination-control signal.
8. The memory module of claim 1 , wherein the first logical combination is the second logical combination.
9. The memory module of claim 1 , wherein each of the memory devices in the first rank of memory devices and the second rank of memory devices comprises dynamic random-access memory.
10. A memory module comprising:
a first memory device having a first data port to communicate first data, a first termination-control port to receive a first termination-control signal, and a second termination-control port to receive a second termination-control signal, the first data port exhibiting a first termination impedance responsive to the first termination-control signal and the second termination-control signal; and
a second memory device having a second data port to communicate second data, a third termination-control port to receive the first termination-control signal, and a fourth termination-control port to receive the second termination-control signal, the second data port exhibiting a second termination impedance responsive to the first termination-control signal and the second termination-control signal.
11. The memory module of claim 10 , the memory module including a rank of memory devices, the rank of memory devices including the first and second memory devices.
12. The memory module of claim 11 , wherein the first termination-control port and the second termination-control port connect to the memory devices in the rank of memory devices.
13. The memory module of claim 10 , wherein the first memory device comprises dynamic random-access memory.
14. The memory module of claim 10 , wherein a first termination impedance and the second termination impedance are adjustable.
15. The memory module of claim 10 , the first data port and the second data port exhibiting a third impedance greater than the first termination impedance and the second termination impedance, the third impedance selected responsive to a combination of the first termination-control signal and the second termination-control signal.
16. The memory module of claim 15 , wherein the first termination-control signal and the second termination-control signal are binary signals.
17. A method of conveying write data to a first device on a memory module over a data link connected to the first memory device and a second memory device on the memory module, each of the first memory device and the second memory device having a first termination-control port to receive a first termination-control signal and a second termination-control port to receive a second termination-control signal, the method comprising:
sending a first combination of the first termination-control signal and the second termination-control signal to the first memory device, wherein the first combination applies a first impedance to the data link, wherein the data link exhibits a termination impedance that is a function of the first impedance;
sending a second combination of the first termination-control signal and the second termination-control signal to the second memory device, wherein the second combination applies a second impedance to the data link, wherein the termination impedance is a function of the second impedance; and
sending the write data to the first device with the data link set to the termination impedance.
18. The method of claim 17 , wherein the first termination-control signal and the second termination-control signal are binary signals.
19. The method of claim 18 , wherein the first combination of the first termination-control signal and the second termination-control signal asserts at least one of the first termination control signal and the second termination control signal.
20. The method of claim 19 , wherein the second combination of the first termination-control signal and the second termination-control signal deasserts the at least one of the first termination-control signal and the second termination-control signal.