IP Library › Granted Patent US 12,302,581
Granted Patent B2
US 12,302,581 · App. 18/398,378 · Granted May 13, 2025

Semiconductor memory device and method of manufacturing the same

Inventor: Kyungmin Jang (Yokkaichi, JP)
Assignee: Kioxia Corporation
H10B43/50H01L21/0217H01L21/02266H01L21/02271H10B43/27
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Quick Facts
Patent No.
US 12,302,581
App. No.
18/398,378
Granted
May 13, 2025
Kind
B2
Abstract

According to an embodiment, a semiconductor memory device includes a semiconductor substrate, a control circuit arranged on the semiconductor substrate, and a memory cell array arranged above the control circuit. The memory cell array includes a plurality of three-dimensionally-arranged memory cells, and is controlled by the control circuit. A first nitride layer is arranged between the control circuit and the memory cell array, and a second nitride layer is arranged between the control circuit and the first nitride layer.

Claims (49)

1. A semiconductor memory device, comprising:

a semiconductor substrate;

a transistor disposed on the semiconductor substrate;

a stacked body disposed above the transistor, the stacked body including a plurality of first conductive layers stacked in a first direction, a pillar extending through the plurality of first conductive layers in the first direction and containing a semiconductor layer, and a charge storage film disposed between the plurality of first conductive layers and the semiconductor layer;

a first silicon nitride layer and a second silicon nitride layer disposed above the transistor; and

a conductor extending through the first silicon nitride layer, the second silicon nitride layer, and the plurality of first conductive layers in the first direction and electrically connected to the transistor, wherein

an etching rate of the second silicon nitride layer is different from an etching rate of the first silicon nitride layer.

2. The device according to claim 1 , wherein

the etching rate of the second silicon nitride layer is greater than the etching rate of the first silicon nitride layer.

3. The device according to claim 1 , wherein

a density of the second silicon nitride layer is lower than a density of the first silicon nitride layer.

4. The device according to claim 1 , wherein

a content of hydrogen in the second silicon nitride layer is lower than a content of hydrogen in the first silicon nitride layer.

5. The device according to claim 1 , wherein

the transistor is a MOS transistor, and the MOS transistor includes boron-containing polycrystalline silicon.

6. The device according to claim 1 , wherein

the first silicon nitride layer and the second silicon nitride layer have respective cross sections cut along planes intersecting the first direction, wherein the respective cross sections both have areas which are greater than an area of a cross section of each of the first conductive layers cut along a plane intersecting the first direction.

7. The device according to claim 1 , wherein

the device is a NAND flash memory.

8. A semiconductor memory device, comprising:

a semiconductor substrate;

a transistor disposed on the semiconductor substrate;

a stacked body disposed above the transistor, the stacked body including a plurality of first conductive layers stacked in a first direction, a pillar extending through the plurality of first conductive layers in the first direction and containing a semiconductor layer, and a charge storage film disposed between the plurality of first conductive layers and the semiconductor layer;

a first silicon nitride layer and a second silicon nitride layer disposed above the transistor; and

a conductor extending through the first silicon nitride layer, the second silicon nitride layer, and the plurality of first conductive layers in the first direction and electrically connected to the transistor, wherein

a density of the second silicon nitride layer is different from a density of the first silicon nitride layer.

9. The device according to claim 8 , wherein

the density of the second silicon nitride layer is lower than the density of the first silicon nitride layer.

10. The device according to claim 8 , wherein

the transistor is a MOS transistor, and the MOS transistor includes boron-containing polycrystalline silicon.

11. The device according to claim 8 , wherein

the first silicon nitride layer and the second silicon nitride layer have respective cross sections cut along planes intersecting the first direction, wherein the respective cross sections both have areas which are greater than an area of a cross section of each of the first conductive layers cut along a plane intersecting the first direction.

12. The device according to claim 8 , wherein

the device is a NAND flash memory.

13. A semiconductor memory device, comprising:

a semiconductor substrate;

a transistor disposed on the semiconductor substrate;

a stacked body disposed above the transistor, the stacked body including a plurality of first conductive layers stacked in a first direction, a pillar extending through the plurality of first conductive layers in the first direction and containing a semiconductor layer, and a charge storage film disposed between the plurality of first conductive layers and the semiconductor layer;

a first silicon nitride layer and a second silicon nitride layer disposed above the transistor; and

a conductor extending through the first silicon nitride layer, the second silicon nitride layer, and the plurality of first conductive layers in the first direction and electrically connected to the transistor, wherein

a content of hydrogen in the second silicon nitride layer is different from a content of hydrogen in the first silicon nitride layer.

14. The device according to claim 13 , wherein

the content of hydrogen in the second silicon nitride layer is lower than the content of hydrogen in the first silicon nitride layer.

15. The device according to claim 13 , wherein

the transistor is a MOS transistor, and the MOS transistor includes boron-containing polycrystalline silicon.

16. The device according to claim 13 , wherein

the first silicon nitride layer and the second silicon nitride layer have respective cross sections cut along planes intersecting the first direction, wherein the respective cross sections both have areas which are greater than an area of a cross section of each of the first conductive layers cut along a plane intersecting the first direction.

17. The device according to claim 13 , wherein

the device is a NAND flash memory.

Priority Claims (1)
JP 2019-166165 · Sep 12, 2019 · national
Continuity (3)
Continuation 17869826 · Jul 21, 2022
Continuation 16797285 · Feb 21, 2020
Related Publication 20240130135A1 · Apr 18, 2024
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