Systems and methods for performing 16-bit floating-point matrix dot product instructions
Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (m, n) of the specified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the specified first source matrix by a corresponding nibble of a doubleword element (K,N) of the specified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element.
1. A processor comprising:
an instruction cache to store a matrix multiplication instruction;
a plurality of vector registers to store a plurality of single-precision floating point source data elements of a first matrix comprising M rows by N columns, a first plurality of bfloat16 floating-point source data elements of a second matrix comprising M rows and K columns, and a second plurality of bfloat16 floating point source data elements of a third matrix comprising K rows by N columns;
decode circuitry to decode the matrix multiplication instruction, the matrix multiplication instruction including an opcode to indicate a matrix multiplication operation, a first field to indicate a first storage location associated with the plurality of single-precision floating point source data elements, a second field to indicate a second storage location associated with the first plurality of bfloat16 floating-point source data elements, and a third field to indicate a third storage location associated with the second plurality of bfloat16 floating point source data elements, wherein the first, second, and third storage locations are locations in the plurality of vector registers; and
execution circuitry coupled with the decode circuitry, the execution circuitry to perform operations in accordance with the matrix multiplication instruction, the execution circuitry to, for each row m of the M rows of the second matrix and each column n of the N columns of the third matrix:
generate a dot product from K bfloat16 floating-point source data elements corresponding to the row m of the second matrix and K bfloat16 floating-point source data elements corresponding to the column n of the third matrix, and
accumulate the dot product with a single precision floating-point source data element corresponding to a row m of the M rows and a column n of the N columns of the first matrix to generate a single-precision floating-point result data element to be stored in a position of the plurality of vector registers corresponding to the row m and the column n of the first matrix.
2. The processor of claim 1 , wherein the execution circuitry comprises:
a plurality of multipliers to multiply the K bfloat16 floating-point source data elements corresponding to the row m of the second matrix and corresponding K bfloat16 floating-point source data elements corresponding to the column n of the third matrix to generate a plurality of products; and
adder circuitry to add the plurality of products to generate the dot product.
3. The processor of claim 2 , wherein the adder circuitry is additionally to add the dot product and the single precision floating-point source data element.
4. The processor of claim 1 , further comprising: a control register to store an indication of a rounding mode.
5. The processor of claim 4 , wherein the execution circuitry is to perform rounding based on instruction fields of some of the instructions regardless of the indication stored in the control register.
6. The processor of claim 1 , wherein the execution circuitry does not support exceptions due to the matrix multiplication instruction.
7. The processor of claim 1 , wherein the execution circuitry is to perform an operation corresponding to the matrix multiplication instruction to process denormal values of the second matrix and the third matrix as zero.
8. The processor of claim 1 , wherein the execution circuitry is to perform an operation corresponding to the instruction to flush denormal values to zero.
9. The processor of claim 1 , wherein the M rows of the second matrix and the N columns of the third matrix are equal in number.
10. The processor of claim 1 , wherein each dot product is a single precision floating-point dot product.
11. A method comprising:
storing a matrix multiplication instruction to an instruction cache;
storing a plurality of single-precision floating point source data elements of a first matrix comprising M rows by N columns, a first plurality of bfloat16 floating-point source data elements of a second matrix comprising M rows and K columns, and a second plurality of bfloat16 floating point source data elements of a third matrix comprising K rows by N columns in a plurality of vector registers;
decoding the matrix multiplication instruction by decode circuitry, wherein the matrix multiplication instruction includes an opcode to indicate a matrix multiplication operation, a first field to indicate a first storage location associated with the plurality of single-precision floating point source data elements, a second field to indicate a second storage location associated with the first plurality of bfloat 16 floating-point source data elements, and a third field to indicate a third storage location associated with the second plurality of bfloat16 floating point source data elements, wherein the first, second, and third storage locations are locations in the plurality of vector registers; and
executing, by execution circuitry coupled with the decode circuitry, the matrix multiplication instruction, wherein the executing is to, for each row m of the M rows of the second matrix and each column n of the N columns of the third matrix:
generate a dot product from K bfloat 16 floating-point source data elements corresponding to the row m of the second matrix and K bfloat16 floating-point source data elements corresponding to the column n of the third matrix, and
accumulate the dot product with a single precision floating-point source data element corresponding to a row m of the M rows and a column n of the N columns of the first matrix to generate a single-precision floating-point result data element to be stored in a position of the plurality of vector registers corresponding to the row m and the column n of the first matrix.
12. The method of claim 11 , wherein the executing comprises:
multiplying, by a plurality of multipliers of the execution circuitry, the K bfloat16 floating-point source data elements corresponding to the row m of the second matrix and corresponding K bfloat16 floating-point source data elements corresponding to the column n of the third matrix to generate a plurality of products; and
adding, by adder circuitry of the execution circuitry, the plurality of products to generate the dot product.
13. The method of claim 12 , wherein the adder circuitry adds the dot product and the single precision floating-point source data element.
14. The method of claim 11 , further comprising storing an indication of a rounding mode in a control register.
15. The method of claim 14 , wherein the executing by the execution circuitry performs rounding based on instruction fields of some of the instructions regardless of the indication stored in the control register.
16. The method of claim 11 , wherein the execution circuitry does not support exceptions due to the matrix multiplication instruction.
17. The method of claim 11 , wherein the executing by the execution circuitry processes denormal values of the second matrix and the third matrix as zero.
18. The method of claim 11 , the executing by the execution circuitry flushes denormal values to zero.
19. The method of claim 11 , wherein the M rows of the second matrix and the N columns of the third matrix are equal in number.
20. The method of claim 11 , wherein each dot product is a single precision floating-point dot product.