IP Library › Granted Patent US 12,308,215
Granted Patent B2
US 12,308,215 · App. 17/701,813 · Granted May 20, 2025

Semiconductor manufacturing apparatus member and semiconductor manufacturing apparatus

Inventors: Ryunosuke Nakagawa (Kitakyushu, JP); Nobutomo Otsuka (Kitakyushu, JP); Tatsuya Koga (Kitakyushu, JP)
Assignee: Toto, Ltd.
H01J37/32495H01J37/32467
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Quick Facts
Patent No.
US 12,308,215
App. No.
17/701,813
Granted
May 20, 2025
Kind
B2
Abstract

According to one embodiment, a semiconductor manufacturing apparatus member is used inside a chamber of a semiconductor manufacturing apparatus. The member includes a base material and a ceramic layer. The base material includes a first surface, a second surface at a side opposite to the first surface, and at least one hole extending through the first and second surfaces. The ceramic layer is a ceramic layer located on the base material. The at least one hole includes a first hole part continuous with the first surface. The ceramic layer includes a first part and a second part. The first part is located on the first surface. The first part is exposed. The second part is located on the first hole part. An arithmetical mean height Sa of a surface of the first part is less than an arithmetical mean height Sa of a surface of the second part.

Claims (48)

1. A semiconductor manufacturing apparatus member used inside a chamber of a semiconductor manufacturing apparatus, the semiconductor manufacturing apparatus member comprising:

a base material including

a first surface,

a second surface at a side opposite to the first surface, and

at least one hole extending through the first and second surfaces; and

a ceramic layer located on the base material,

the at least one hole including a first hole part continuous with the first surface,

the ceramic layer including

a first part located on the first surface, the first part being exposed, and

a second part located on the first hole part,

an arithmetical mean height Sa of a surface of the first part being less than an arithmetical mean height Sa of a surface of the second part,

wherein the arithmetical mean height Sa of the surface of the first part is a surface roughness of the surface of the first part; and the arithmetical mean height Sa of the surface of the second part is a surface roughness of the surface of the second part.

2. The semiconductor manufacturing apparatus member according to claim 1 , wherein

the at least one hole further includes:

a second hole part positioned between the second surface and the first hole part in a first direction, the first direction being from the first surface toward the second surface; and

a third hole part positioned between the first hole part and the second hole part in the first direction, the third hole part being continuous with the first hole part and being exposed, and

an arithmetical mean height Sa of the third hole part is greater than the arithmetical mean height Sa of the surface of the first part and greater than the arithmetical mean height Sa of the surface of the second part.

3. The semiconductor manufacturing apparatus member according to claim 2 , wherein

the arithmetical mean height Sa of the third hole part is greater than 2 times the arithmetical mean height Sa of the surface of the first part.

4. The semiconductor manufacturing apparatus member according to claim 1 , wherein

the arithmetical mean height Sa of the surface of the second part is not more than 10 times the arithmetical mean height Sa of the surface of the first part.

5. The semiconductor manufacturing apparatus member according to claim 1 , wherein

the arithmetical mean height Sa of the surface of the second part is less than 0.5 micrometers.

6. The semiconductor manufacturing apparatus member according to claim 1 , wherein

the arithmetical mean height Sa of the surface of the first part is less than 0.1 micrometers.

7. The semiconductor manufacturing apparatus member according to claim 1 , wherein

the at least one hole further includes:

a second hole part positioned between the second surface and the first hole part in a first direction, the first direction being from the first surface toward the second surface; and

a third hole part positioned between the first hole part and the second hole part in the first direction, the third hole part being continuous with the first hole part and being exposed, and

an arithmetical mean height Sa of the third hole part is greater than the arithmetical mean height Sa of the surface of the first part and less than the arithmetical mean height Sa of the surface of the second part.

8. The semiconductor manufacturing apparatus member according to claim 1 , wherein

the ceramic layer includes a polycrystalline ceramic.

9. The semiconductor manufacturing apparatus member according to claim 8 , wherein

an average crystallite size of the polycrystalline ceramic calculated using a TEM image having a magnification of 400,000 times to 2,000,000 times is not less than 3 nanometers and not more than 50 nanometers.

10. The semiconductor manufacturing apparatus member according to claim 1 , wherein

the ceramic layer includes at least one selected from the group consisting of an oxide of a rare-earth element, a fluoride of a rare-earth element, and an acid fluoride of a rare-earth element.

11. The semiconductor manufacturing apparatus member according to claim 10 , wherein

the rare-earth element is at least one selected from the group consisting of Y, Sc, Yb, Ce, Pr, Eu, La, Nd, Pm, Sm, Gd, Tb, Dy, Ho, Er, Tm, and Lu.

12. The semiconductor manufacturing apparatus member according to claim 1 , wherein

the base material includes a ceramic.

13. The semiconductor manufacturing apparatus member according to claim 12 , wherein

the base material includes alumina.

14. A semiconductor manufacturing apparatus, comprising:

a chamber; and

the semiconductor manufacturing apparatus member according to claim 1 ,

the chamber including an interior wall,

the interior wall defining a space in which plasma is generated,

the ceramic layer of the semiconductor manufacturing apparatus member being included in at least a portion of the interior wall.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2022
From: NAKAGAWA, RYUNOSUKE; OTSUKA, NOBUTOMO; KOGA, TATSUYA
To: TOTO LTD.
Reel/Frame 059695/0387 →
Priority Claims (2)
JP 2021-072039 · Apr 21, 2021 · national
JP 2022-011203 · Jan 27, 2022 · national
Continuity (1)
Related Publication 20220351944A1 · Nov 3, 2022
References Cited (17)
US 11749507B2 · Nakagawa · 2023 [cited by examiner]
US 20120037596A1 · Eto et al. · 2012 [cited by applicant]
US 20120040132A1 · Eto et al. · 2012 [cited by applicant]
US 20160010200A1 · Mitsuhashi et al. · 2016 [cited by applicant]
US 20200273675A1 · Nitta et al. · 2020 [cited by applicant]
JP 4544700B2 · 2010 [cited by examiner]
JP 2012057251A · 2012 [cited by applicant]
JP 2012060101A · 2012 [cited by applicant]
JP 2016028379A · 2016 [cited by applicant]
JP 2020141123A · 2020 [cited by examiner]
KR 1020200104811A · 2020 [cited by applicant]
TW 1306282B · 2009 [cited by examiner]
TW 201708602A · 2017 [cited by examiner]
English Translation JP-2020141123-A (Year: 2020). [cited by examiner]
English Translation TW-201708602-A (Year: 2017). [cited by examiner]
English Translation JP-4544700B2 (Year: 2010). [cited by examiner]
English Translation TW-1306282 (Year: 2009). [cited by examiner]