Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices
Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.
1. An integrated circuit structure, comprising:
a first semiconductor body;
a second semiconductor body vertically over the first semiconductor body, the second semiconductor body vertically spaced apart from the first semiconductor body by an insulating layer;
a gate structure over the second semiconductor body and the first semiconductor body, the gate structure having a first side and a second side, the first side opposite the second side;
a first source or drain structure coupled to the first semiconductor body and the second semiconductor body at the first side of the gate structure;
a second source or drain structure coupled to the first semiconductor body and the second semiconductor body at the second side of the gate structure;
a first conductive contact structure extending from a top of the first source or drain structure into the first source or drain structure to a first depth; and
a second conductive contact structure extending from a top of the second source or drain structure into the second source or drain structure to a second depth, the second depth less than the first depth.
2. The integrated circuit structure of claim 1 , wherein the first conductive contact structure is laterally adjacent to the second semiconductor body and the first semiconductor body.
3. The integrated circuit structure of claim 1 , wherein the second conductive contact structure is laterally adjacent to the second semiconductor body but is not laterally adjacent to the first semiconductor body.
4. The integrated circuit structure of claim 1 , wherein the first conductive contact structure is laterally adjacent to the second semiconductor body and the first semiconductor body, and wherein the second conductive contact structure is laterally adjacent to the second semiconductor body but is not laterally adjacent to the first semiconductor body.
5. The integrated circuit structure of claim 1 , further comprising:
a third conductive contact structure extending from a bottom of the second source or drain structure into the second source or drain structure toward the second conductive contact structure but not in contact with the second conductive contact structure.
6. The integrated circuit structure of claim 5 , wherein the third conductive contact structure is laterally adjacent to the first semiconductor body but is not laterally adjacent to the second semiconductor body.
7. The integrated circuit structure of claim 1 , wherein the insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material having a different composition than the first dielectric material.
8. The integrated circuit structure of claim 1 , further comprising:
a first gate spacer between the first side of the gate structure and the first source or drain region; and
a second gate spacer between the second side of the gate structure and the second source or drain region.
9. The integrated circuit structure of claim 8 , wherein an uppermost surface of the gate structure, an uppermost surface of the first gate spacer, an uppermost surface of the second gate spacer, an uppermost surface of the first conductive contact structure, and an uppermost surface of the second conductive contact structure are co-planar with one another.
10. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first semiconductor body;
a second semiconductor body vertically over the first semiconductor body, the second semiconductor body vertically spaced apart from the first semiconductor body by an insulating layer;
a gate structure over the second semiconductor body and the first semiconductor body, the gate structure having a first side and a second side, the first side opposite the second side;
a first source or drain structure coupled to the first semiconductor body and the second semiconductor body at the first side of the gate structure;
a second source or drain structure coupled to the first semiconductor body and the second semiconductor body at the second side of the gate structure;
a first conductive contact structure extending from a top of the first source or drain structure into the first source or drain structure to a first depth; and
a second conductive contact structure extending from a top of the second source or drain structure into the second source or drain structure to a second depth, the second depth less than the first depth.
11. The computing device of claim 10 , further comprising:
a memory coupled to the board.
12. The computing device of claim 10 , further comprising:
a communication chip coupled to the board.
13. The computing device of claim 10 , further comprising:
a camera coupled to the board.
14. The computing device of claim 10 , further comprising:
a battery coupled to the board.
15. The computing device of claim 10 , further comprising:
a compass coupled to the board.
16. The computing device of claim 10 , further comprising:
a GPS coupled to the board.
17. The computing device of claim 10 , further comprising:
a speaker coupled to the board.
18. The computing device of claim 10 , further comprising:
a display coupled to the board.
19. The computing device of claim 10 , wherein the component is a packaged integrated circuit die.