Granted Patent B2

US 12,314,129 · App. 18/400,256 · Granted May 27, 2025

Inventors: Sungwon Jeong (Suwon-si, KR); Moonsang Kwon (Seoul, KR); Younghoi Heo (Uijeongbu-si, KR); Jaeshin Lee (Seoul, KR); Eun Jung (Seoul, KR)

Assignee: SAMSUNG ELECTRONICS CO., LTD.

G06F11/1004G06N20/00

Abstract

Claims (40)

1. A storage controller configured to control a non-volatile memory, the storage controller comprising:

a command and address generator configured to generate a first command, an address, and a second command as a command set, the second command including an error detection signal for detecting a communication error in the first command and the address;

an error detection module configured to generate the error detection signal from the first command and the address, so that the non-volatile memory detects the communication error in the first command and the address; and

an interface circuit configured to sequentially transmit the first command, the address, and the second command as the command set to the non-volatile memory,

wherein the first command indicates a type of a memory operation to be performed in the non-volatile memory, and

the second command corresponds to a confirm command related to the memory operation.

2. The storage controller of claim 1 , wherein the error detection signal comprises a 1-bit signal.

3. The storage controller of claim 1 , wherein the error detection module is further configured to generate a parity bit from the first command and the address, wherein the parity bit is the error detection signal.

4. The storage controller of claim 1 , wherein the error detection module is further configured to generate a cyclic redundancy check (CRC) value from the first command and the address, wherein the CRC value is the error detection signal.

5. The storage controller of claim 1 , wherein the error detection module is further configured to generate a checksum from the first command and the address, wherein the checksum is the error detection signal.

6. The storage controller of claim 1 , wherein the interface circuit is further configured to:

transmit, to the non-volatile memory, a command latch enable signal having an enable level in a transmission period of the first command and the second command; and

transmit, to the non-volatile memory, an address latch enable signal having an enable level in a transmission period of the address.

7. The storage controller of claim 1 , wherein the interface circuit is further configured to:

receive an error message from the non-volatile memory when the communication error is detected.

8. The storage controller of claim 7 , wherein the interface circuit sequentially transmits the first command, the address, and the second command again to the non-volatile memory based on the error message.

9. A non-volatile memory device comprising:

an interface circuit configured to sequentially receive a first command, an address, and a second command as a command set from a storage controller, the second command including an error detection signal for detecting a communication error in the first command and the address;

a memory cell array including a plurality of memory cells; and

a control logic circuitry configured to detect the communication error in the first command and the address, based on the error detection signal,

wherein the first command indicates a type of a memory operation to be performed in the non-volatile memory device, and

the second command corresponds to a confirm command related to the memory operation.

10. The non-volatile memory device of claim 9 , wherein the error detection signal comprises a 1-bit signal.

11. The non-volatile memory device of claim 9 , wherein the error detection signal comprises a parity bit generated from the first command and the address.

12. The non-volatile memory device of claim 9 , wherein the error detection signal comprises a cyclic redundancy check (CRC) value generated from the first command and the address.

13. The non-volatile memory device of claim 9 , wherein the error detection signal comprises a checksum generated from the first command and the address.

14. The non-volatile memory device of claim 9 , wherein the interface circuit is further configured to transmit an error message to the storage controller when the communication error is detected.

15. An operating method of a storage controller configured to control a non-volatile memory, the operating method comprising:

generating a first command and an address;

generating an error detection signal from the first command and the address, so that the non-volatile memory detects a communication error in the first command and the address;

generating a confirm command including the error detection signal; and

sequentially transmitting the first command, the address, and the confirm command as a command set to the non-volatile memory,

wherein the first command includes a read command or a write command, and

the confirm command is related to a read operation corresponding to the read command or a write operation corresponding to the write operation.

16. The operating method of claim 15 , wherein the generating of the error detection signal comprises: generating the error detection signal including a 1-bit signal.

17. The operating method of claim 15 , wherein the generating of the error detection signal comprises: generating the error detection signal including a parity bit from the first command and the address.

18. The operating method of claim 15 , wherein the generating of the error detection signal comprises: generating the error detection signal including a cyclic redundancy check (CRC) value from the first command and the address.

19. The operating method of claim 15 , wherein the generating of the error detection signal comprises: generating the error detection signal including a checksum from the first command and the address.

20. The operating method of claim 15 , further comprising:

receiving an error message from the non-volatile memory when the communication error is detected.

Priority Claims (1)

Continuity (3)

References Cited (28)