Providing a memory device having a shared error feedback pin
A system and method for providing a memory device having a shared error feedback pin. The system includes a memory device having a data interface configured to receive data bits and CRC bits, CRC receiving circuitry, CRC creation circuitry, a memory device pad, and driver circuitry. The CRC receiving circuitry utilizes a CRC equation for the detection of errors in one or more of the received data and the received CRC bits. The CRC creation circuitry utilizes the CRC equation for the creation of CRC bits consistent with data to be transmitted to a separate device bits. The memory device pad is configured for reporting of any errors detected in the received data and the received CRC bits. The driver circuitry is connected to the memory device pad and merged with one or more other driver circuitries resident on one or more other memory devices into an error reporting line.
1. A memory device comprising a receiver, a driver circuitry, and an error pin that is shared by the memory device and at least one other memory device, the memory device configured to perform a method comprising:
receiving, via the receiver, write data and cyclical redundancy code (CRC) bits from a memory controller;
generating CRC bits responsive to the write data;
comparing the received CRC bits to the generated CRC bits;
based on determining that the received CRC bits are not equal to the generated CRC bits, generating, by the driver circuitry, an error signal; and
based on determining that there is no error based on the received CRC bits being equal to the generated CRC bits, completing a write operation to the memory device.
2. The memory device of claim 1 , wherein generating the error signal comprises outputting the error signal from the memory device via the error pin.
3. The memory device of claim 2 , further comprising reporting, via the error pin, an existence of parity or other errors associated with address and command information received by the memory device.
4. The memory device of claim 1 , wherein the error signal is transmitted to the memory controller.
5. The memory device of claim 1 , wherein the received CRC bits are generated responsive to the data and to a CRC polynomial equation, and the generating, by a memory device, CRC bits is further responsive to the CRC polynomial equation.
6. The memory device of claim 1 , wherein the memory device is located on a memory module that includes at least one other memory device.
7. The memory device of claim 1 , wherein the data and CRC bits are received over multiple transfers, the multiple transfers comprising a packet of information.
8. A method comprising:
receiving write data and cyclical redundancy code (CRC) bits from a memory controller;
generating, by a memory device, CRC bits responsive to the write data;
comparing, by the memory device, the received CRC bits to the generated CRC bits;
based on determining that the received CRC bits are not equal to the generated CRC bits, generating, by the memory device, an error signal;
based on determining that there is no error based on the received CRC bits being equal to the generated CRC bits, completing a write operation to the memory device; and
wherein generating the error signal comprises outputting the error signal from the memory device via an error pin that is shared by the memory device and at least one other memory device.
9. The method of claim 8 , further comprising reporting, via the error pin, an existence of parity or other errors associated with address and command information received by the memory device.
10. The method of claim 8 , wherein the error signal is transmitted to the memory controller.
11. The method of claim 8 , wherein the received CRC bits are generated responsive to the data and to a CRC polynomial equation, and the generating, by a memory device, CRC bits is further responsive to the CRC polynomial equation.
12. The method of claim 8 , wherein the memory device is located on a memory module that includes at least one other memory device.
13. The method of claim 8 , wherein the data and CRC bits are received over multiple transfers, the multiple transfers comprising a packet of information.
14. A computer program product for writing to a memory device, the computer program product comprising:
a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
receiving, via the receiver, write data and cyclical redundancy code (CRC) bits from a memory controller;
generating CRC bits responsive to the write data;
comparing the received CRC bits to the generated CRC bits;
based on determining that the received CRC bits are not equal to the generated CRC bits, generating, by the driver circuitry, an error signal; and
based on determining that there is no error based on the received CRC bits being equal to the generated CRC bits, completing a write operation to the memory device; and
wherein generating the error signal comprises outputting the error signal from the memory device via an error pin that is shared by the memory device and at least one other memory device.
15. The computer program product of claim 14 , wherein the method further comprises reporting, via the error pin, an existence of parity or other errors associated with address and command information received by the memory device.
16. The computer program product of claim 14 , wherein the error signal is transmitted to the memory controller.
17. The computer program product of claim 14 , wherein the memory device is located on a memory module that includes at least one other memory device.
18. The computer program product of claim 14 , wherein the data and CRC bits are received over multiple transfers, the multiple transfers comprising a packet of information.