Memory device bandwidth optimization
Techniques for scheduling memory operations are disclosed in which alternate read/write commands within a multi-bank memory operation are delayed beyond a minimum timing parameter in order to increase memory data bus utilization. The remaining read/write commands are not delayed beyond the minimum timing parameter. Every other clock cycle (e.g., even clock cycles) within the memory operation is reserved for activate commands, while other commands such as sync and read/write are scheduled on the intervening clock cycles (e.g., odd clock cycles). For memory devices for which a sync command (which causes a clock of the memory data bus to start) is to precede a corresponding read/write command by a number of clock cycles that would place it in a cycle reserved for activate commands, a particular operation mode is disclosed in which the memory device internally delays a received sync command.
1. An apparatus, comprising:
a memory device that includes:
a plurality of memory bank circuits, a given memory bank circuit of the plurality of memory bank circuits including a respective set of memory cell circuits;
a command bus circuit configured to receive a plurality of memory commands;
a data bus circuit configured to transfer data to and from one or more of the memory cell circuits in response to ones of the plurality of memory commands; and
wherein the memory device is configured to:
receive, via the command bus circuit, a sync command executable to start a clock signal of the data bus circuit;
based on having received an indication of a sync delay, start the clock signal of the data bus circuit after a delay period; and
based on not having received the indication of the sync delay, start the clock signal of the data bus circuit without the delay period.
2. The apparatus of claim 1 , wherein the indication of the sync delay is a sync delay command, and wherein the memory device is configured to enter a sync delay mode based on receiving the sync delay command.
3. The apparatus of claim 1 , wherein the sync command includes an operand indicative of a number of command bus cycles to wait before the clock signal of the data bus circuit is started; and
wherein the memory device is further configured to determine whether the sync delay is indicated based on a value of the operand.
4. The apparatus of claim 3 , wherein the indication of the sync delay is a non-zero value of the operand of the sync command.
5. The apparatus of claim 4 , wherein the memory device includes a multi-bit counter circuit; and
wherein the memory device is further configured to use the operand with the multi-bit counter circuit to implement any indicated delay period.
6. The apparatus of claim 1 , wherein the memory device pipeline circuit includes a command decode circuit and a command execution circuit.
7. The apparatus of claim 6 , wherein the command decode circuit is configured to:
decode the sync command; and
route the sync command to the command execution circuit after any indicated delay period.
8. The apparatus of claim 6 , wherein the command decode circuit is configured to:
decode the sync command; and
route the sync command to the command execution circuit; and
wherein the command execution circuit is configured to:
based at least on an indication of the sync delay, start the clock signal of the data bus circuit after any indicated delay period; and
based at least on a lack of an indication of the sync delay, start the clock signal of the data bus circuit without the delay period.
9. A method, comprising:
receiving, by a memory circuit over a first plurality of command bus cycles, a particular series of commands for accessing a plurality of memory banks in the memory circuit, including:
receiving a set of activation commands for a particular memory bank of the plurality of memory banks;
receiving, after a particular number of command bus cycles from receiving the set of activation commands, a sync command; and
based at least on an indication of a sync delay mode, activating a data bus clock signal after a delay of one or more command bus cycles from receiving the sync command.
10. The method of claim 9 , further comprising:
receiving, by the memory circuit over a second plurality of command bus cycles, a different series of commands for accessing the plurality of memory banks in the memory circuit, including:
receiving a different set of activation commands for the particular memory bank;
receiving, after a different number of command bus cycles from receiving the different set of activation commands, a different sync command; and
activating, on a subsequent command bus cycle without a delay, the data bus clock signal.
11. The method of claim 9 , further comprising receiving, after the delay of one or more command bus cycles, a read command for the particular memory bank.
12. The method of claim 11 , further comprising sending, on a data bus using the activated data bus clock signal, data requested by the read command.
13. The method of claim 9 , wherein the sync command includes an indication of a number of command bus cycles to delay before starting the data bus clock signal.
14. The method of claim 9 , further comprising receiving, prior to receiving the particular series of commands, an indication to enter the sync delay mode.
15. An apparatus, comprising:
a memory interface circuit configured to couple to a memory device via a command bus including a command clock signal and a data bus including a data clock signal, wherein the memory device includes a plurality of memory banks; and
a control circuit coupled to the memory interface circuit and configured to:
send a set of activate commands that indicate a particular memory bank of the memory device;
send, a number of command clock cycles after the last of the set of activation commands is sent, a sync command that causes the memory device to start the data clock signal; and
send, after a determined number of command clock cycles, a read command for the particular memory bank.
16. The apparatus of claim 15 , wherein the determined number of cycles is greater than one.
17. The apparatus of claim 15 , wherein the control circuit is further configured to include an operand in the sync command, wherein the operand indicates the determined number of command clock cycles to pause.
18. The apparatus of claim 17 , wherein the control circuit is further configured to omit the operand in the sync command, and wherein omitting the operand causes the memory device to start the data clock signal without a delay.
19. The apparatus of claim 15 , wherein the control circuit is further configured to include, prior to the sync command being sent, a sync delay mode command, wherein the sync delay mode command causes the memory device to insert a pause before the data clock signal is started.
20. The apparatus of claim 15 , wherein the control circuit is further configured to receive, on the data bus using the data clock signal, data requested by the read command.