Embedded semiconductor packages and methods thereof
Semiconductor packages and, more particularly, chip-embedded semiconductor packages. The packages include core panels with apertures extending through the core panel. Semiconductor chips are embedded within chip apertures. A molding compound can be positioned along one side of the core panel. The semiconductor chips can be embedded within the molding compound. The semiconductor chips also can be adhered to the molding compound. The coefficient of thermal expansion (CTE) values of the core panels can be tailored to decrease warpage of the package as the semiconductor chip heats during use.
1. A method of manufacturing an embedded semiconductor package comprising:
disposing a first semiconductor chip in a first chip aperture extending from a first side of a core panel to a second side of the core panel and at least partially within a molding compound layer, a second chip aperture, and a third chip aperture, each extending from the first side to the second side of the core panel, and the molding compound layer having a first side and a second side, the first side of the molding compound layer proximate the first side of the core panel and extending at least partially into the first chip aperture;
disposing a second semiconductor chip in the third chip aperture of the core panel and at least partially within the molding compound layer;
positioning a first dielectric layer proximate the second side of the core panel and proximate a first electrode;
disposing a first redistribution layer within the first dielectric layer and in electrical communication with the first electrode;
positioning a second dielectric layer proximate to and in contact with the second side of the molding compound layer; and
disposing a second redistribution layer disposed within the second dielectric layer and in electrical communication with the first redistribution layer.
2. The method of claim 1 , wherein:
the first semiconductor chip has a first side proximate the molding compound layer and a second side opposite the molding compound layer and proximate the second side of the core panel;
the second side of the first semiconductor chip has the first electrode; and
a second semiconductor chip disposed in the third chip aperture and at least partially within the molding compound layer.
3. The method of claim 2 further comprising:
extending a conductive material through the second chip aperture;
wherein the conductive material has a first end in electrical communication with the first redistribution layer and a second end in electrical communication with the second redistribution layer.
4. A method of manufacturing an embedded semiconductor package comprising:
preparing a core panel having a first side and a second side, the core panel comprising a first chip aperture extending from the first side to the second side of the core panel;
attaching the first side of the core panel to a carrier layer with an adhesive;
forming a molding compound layer having a first side and a second side to the core panel, wherein the first side of the molding compound layer is proximate the first side of the core panel and extends at least partially into the first chip aperture;
placing a first semiconductor chip into the first chip aperture and at least partially within the molding compound layer, the first semiconductor chip having a first side proximate the molding compound layer and a second side opposite the molding compound layer and proximate the second side of the core panel, and the first semiconductor chip further having a first electrode proximate the carrier layer;
removing the carrier layer and the adhesive from the first side of the core panel;
applying a first dielectric layer to the first side of the core panel;
applying a second dielectric layer to the molding compound layer;
creating a second chip aperture in the core panel and the molding compound layer, the second chip aperture extending from the first dielectric layer to the second dielectric layer;
metalizing a wall of the second chip aperture;
forming a first redistribution layer on the first dielectric layer, the first redistribution layer in electrical communication with the first electrode and with a first end of the metalized wall; and
forming a second redistribution layer on the second dielectric layer, the second redistribution layer in electrical communication with a second end of the metalized wall.
5. The method of claim 4 further comprising:
creating a third chip aperture in the core panel and the molding compound layer, the third chip aperture extending from the first dielectric layer to the second dielectric layer; and
placing a second semiconductor chip into the third chip aperture and at least partially within the molding compound layer.
6. The method of claim 5 further comprising:
applying a third dielectric layer to cover the first redistribution layer; and
applying a fourth dielectric layer to cover the second redistribution layer.
7. The method of claim 5 , wherein the core panel has a coefficient of thermal expansion in a range between that of the first semiconductor chip and the molding compound layer.
8. The method of claim 5 , wherein the core panel comprises glass.
9. The method of claim 8 , wherein the glass has a coefficient of thermal expansion of approximately 3 ppm/° C. to 18 ppm/° C.
10. The method of claim 5 , wherein the core panel comprises at least one of an organic laminate material or an inorganic laminate material.
11. The method of claim 5 , wherein the core panel comprises at least one of quartz or a metallic material.
12. The method of claim 5 , wherein the core panel has a thickness of less than 100 μm.
13. The method of claim 5 , wherein:
the core panel does not extend over the first semiconductor chip; and
the embedded semiconductor package does not include an additional core panel parallel to the core panel.
14. A method of manufacturing an embedded semiconductor package comprising:
preparing a core panel having a first side and a second side, the core panel comprising a first chip aperture extending from the first side to the second side of the core panel;
preparing a layer of molding compound, thereby forming a molding compound layer;
placing the first side of the core panel on the molding compound layer;
curing the molding compound;
placing a first semiconductor chip into the first chip aperture, the first semiconductor chip having a first side and a second side, the second side having a first electrode;
adhering the first side of the first semiconductor chip to the molding compound layer;
applying a first dielectric layer to the second side of the core panel;
applying a second dielectric layer to the molding compound layer;
creating a second chip aperture in the core panel and the molding compound layer, the second chip aperture extending from the first dielectric layer to the second dielectric layer;
creating a third chip aperture in the core panel extending from the first side to the second side of the core panel;
placing a second semiconductor chip into the third chip aperture, the second semiconductor chip having a first side and a second side, the second side having a second electrode;
adhering the first side of the second semiconductor chip to the molding compound layer;
metalizing a wall of the second chip aperture;
forming a first redistribution layer on the first dielectric layer, the first redistribution layer in electrical communication with the first electrode and with a first end of the metalized wall; and
forming a second redistribution layer on the second dielectric layer, the second redistribution layer in electrical communication with a second end of the metalized wall.
15. The method of claim 14 , wherein adhering the first side of the first semiconductor chip to the molding compound layer comprises placing a die attach film between the first side of the first semiconductor chip and the molding compound layer.
16. The method of claim 14 , wherein adhering the first side of the second semiconductor chip to the molding compound layer comprises placing a die attach film between the first side of the second semiconductor chip and the molding compound layer.
17. The method of claim 14 further comprising:
applying a third dielectric layer to cover the first redistribution layer; and
applying a fourth dielectric layer to cover the second redistribution layer.
18. The method of claim 14 , wherein curing the molding compound comprises:
curing the molding compound at a first temperature; and
subsequent to curing the molding compound at the first temperature, curing the molding compound at a second temperature;
wherein the first temperature is lower than the second temperature.
19. The method of claim 14 , wherein the core panel has a coefficient of thermal expansion in a range between that of the first semiconductor chip and the molding compound layer.
20. The method of claim 14 , wherein at least one of:
the core panel comprises glass;
the core panel comprises glass having a coefficient of thermal expansion of approximately 3 ppm/° C. to 18 ppm/° C.;
the core panel comprises an organic laminate material;
the core panel comprises an inorganic laminate material;
the core panel comprises quartz;
the core panel comprises a metallic material;
the core panel has a thickness of less than 100 μm;
the core panel does not extend over the first semiconductor chip; or
the embedded semiconductor package does not include an additional core panel parallel to the core panel.