IP Library Granted Patent US 12,317,544
Granted Patent B2
US 12,317,544 · App. 18/132,527 · Granted May 27, 2025

Semiconductor device

Inventors: Junichi Koezuka (Tochigi, JP); Kenichi Okazaki (Tochigi, JP); Yasuharu Hosaka (Tochigi, JP); Toshimitsu Obonai (Shimotsuke, JP); Yasutaka Nakazawa (Tochigi, JP); Seiji Yasumoto (Tochigi, JP); Shunpei Yamazaki (Setagaya, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10D30/6755H10D30/6757H10D30/6758H10D86/423H10D86/60H05B33/22H10K50/00
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,317,544
App. No.
18/132,527
Granted
May 27, 2025
Kind
B2
Abstract

A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor device with stable electrical characteristics is provided. A semiconductor device includes a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer. The semiconductor layer, the second insulating layer, and the first conductive layer are stacked in this order over the first insulating layer. The second insulating layer has a stacked-layer structure in which a first insulating film, a second insulating film, and a third insulating film are stacked in this order. The first insulating film, the second insulating film, and the third insulating film each contain an oxide. The first insulating film includes a portion in contact with the semiconductor layer. The semiconductor layer contains indium, gallium, and oxygen and includes a region with an indium content percentage higher than a gallium content percentage.

Claims (54)

1. A semiconductor device comprising a transistor comprising:

a first insulating layer;

an oxide semiconductor layer comprising a channel formation region, a source region, and a drain region of the transistor over the first insulating layer;

a second insulating layer over the oxide semiconductor layer;

a gate electrode over the second insulating layer;

a third insulating layer over the gate electrode; and

a source electrode and a drain electrode over the third insulating layer,

wherein the gate electrode overlaps with the channel formation region with the second insulating layer therebetween,

wherein the source electrode is in contact with the source region through a first opening in the second insulating layer and the third insulating layer,

wherein the drain electrode is in contact with the drain region through a second opening in the second insulating layer and the third insulating layer,

wherein the second insulating layer comprises a first insulating film in contact with the channel formation region, the source region, and the drain region and a second insulating film over the first insulating film,

wherein the oxide semiconductor layer comprises indium oxide, and

wherein the second insulating layer comprises an oxide.

2. The semiconductor device according to claim 1 , wherein the first insulating film is formed at a lower deposition rate than the second insulating film.

3. The semiconductor device according to claim 1 , further comprising a metal oxide layer between the second insulating layer and the gate electrode,

wherein the metal oxide layer comprises one or more elements selected from aluminum, hafnium, indium, gallium, zinc, tin, and silicon.

4. The semiconductor device according to claim 3 ,

wherein the metal oxide layer comprises indium, and

wherein the metal oxide layer and the oxide semiconductor layer have substantially the same indium content percentage.

5. A semiconductor device comprising a transistor comprising:

a first insulating layer;

a first oxide semiconductor layer over the first insulating layer;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a second insulating layer over the second oxide semiconductor layer;

a gate electrode over the second insulating layer;

a third insulating layer over the gate electrode; and

a source electrode and a drain electrode over the third insulating layer,

wherein the second oxide semiconductor layer comprises a channel formation region, a source region, and a drain region of the transistor,

wherein the gate electrode overlaps with the channel formation region with the second insulating layer therebetween,

wherein the source electrode is in contact with the source region through a first opening in the second insulating layer and the third insulating layer,

wherein the drain electrode is in contact with the drain region through a second opening in the second insulating layer and the third insulating layer,

wherein the second insulating layer comprises a first insulating film in contact with the channel formation region, the source region, and the drain region and a second insulating film over the first insulating film,

wherein the second oxide semiconductor layer comprises indium oxide, and

wherein the second insulating layer comprises an oxide.

6. The semiconductor device according to claim 5 , wherein the first oxide semiconductor layer comprises indium, gallium, and zinc.

7. The semiconductor device according to claim 5 , wherein the first insulating film is formed at a lower deposition rate than the second insulating film.

8. The semiconductor device according to claim 5 , further comprising a metal oxide layer between the second insulating layer and the gate electrode,

wherein the metal oxide layer comprises one or more elements selected from aluminum, hafnium, indium, gallium, zinc, tin, and silicon.

9. The semiconductor device according to claim 8 ,

wherein the metal oxide layer comprises indium, and

wherein the metal oxide layer and the second oxide semiconductor layer have substantially the same indium content percentage.

10. A semiconductor device comprising a transistor comprising:

a first insulating layer;

an oxide semiconductor layer comprising a channel formation region, a source region, and a drain region of the transistor over the first insulating layer;

a second insulating layer over the oxide semiconductor layer;

a gate electrode over the second insulating layer;

a third insulating layer over the gate electrode; and

a source electrode and a drain electrode over the third insulating layer,

wherein the gate electrode overlaps with the channel formation region with the second insulating layer therebetween,

wherein the source electrode is in contact with the source region through a first opening in the second insulating layer and the third insulating layer,

wherein the drain electrode is in contact with the drain region through a second opening in the second insulating layer and the third insulating layer,

wherein the second insulating layer comprises a first insulating film in contact with the channel formation region, the source region, and the drain region, a second insulating film over the first insulating film, and a third insulating film over the second insulating film,

wherein the oxide semiconductor layer comprises indium oxide, and

wherein the second insulating layer comprises an oxide.

Priority Claims (4)
JP 2018-146787 · Aug 3, 2018 · national
JP 2018-175352 · Sep 19, 2018 · national
JP 2018-201126 · Oct 25, 2018 · national
JP 2019-061174 · Mar 27, 2019 · national
Continuity (2)
Continuation 17262793
Related Publication 20230317856A1 · Oct 5, 2023
References Cited (47)
US 9382611B2 · Yamazaki · 2016 [cited by examiner]
US 9443876B2 · Yamazaki et al. · 2016 [cited by applicant]
US 9490368B2 · Kimura et al. · 2016 [cited by applicant]
US 9768279B2 · Noda · 2017 [cited by examiner]
US 9831353B2 · Kawata. et al. · 2017 [cited by applicant]
US 9837547B2 · Koezuka et al. · 2017 [cited by applicant]
US 10249645B2 · Yamazaki et al. · 2019 [cited by applicant]
US 10319861B2 · Koezuka et al. · 2019 [cited by applicant]
US 10468531B2 · Kimura et al. · 2019 [cited by applicant]
US 10811435B2 · Yamazaki et al. · 2020 [cited by applicant]
US 10861981B2 · Koezuka et al. · 2020 [cited by applicant]
US 10903368B2 · Koezuka et al. · 2021 [cited by applicant]
US 11107837B2 · Yamazaki et al. · 2021 [cited by applicant]
US 11450691B2 · Yamazaki et al. · 2022 [cited by applicant]
US 11695078B2 · Koezuka et al. · 2023 [cited by applicant]
US 11699762B2 · Yamazaki et al. · 2023 [cited by applicant]
US 20130161608A1 · Yamazaki · 2013 [cited by applicant]
US 20130320334A1 · Yamazaki et al. · 2013 [cited by applicant]
US 20140103335A1 · Yamazaki et al. · 2014 [cited by applicant]
US 20140319517A1 · Noda · 2014 [cited by examiner]
US 20150263141A1 · Yamazaki et al. · 2015 [cited by applicant]
US 20160343866A1 · Koezuka et al. · 2016 [cited by applicant]
US 20170104090A1 · Koezuka et al. · 2017 [cited by applicant]
US 20170200829A1 · Watakabe et al. · 2017 [cited by applicant]
US 20170301699A1 · Yamazaki et al. · 2017 [cited by applicant]
US 20230005969A1 · Yamazaki et al. · 2023 [cited by applicant]
US 20230343875A1 · Yamazaki et al. · 2023 [cited by applicant]
CN 104821338A · 2015 [cited by applicant]
CN 107017210A · 2017 [cited by applicant]
JP 2008218626A · 2008 [cited by applicant]
JP 2012004549A · 2012 [cited by applicant]
JP 2013149965A · 2013 [cited by applicant]
JP 2014007399A · 2014 [cited by applicant]
JP 2014099599A · 2014 [cited by applicant]
JP 2015188079A · 2015 [cited by applicant]
JP 2017028252A · 2017 [cited by applicant]
JP 2017076768A · 2017 [cited by applicant]
JP 2017076788A · 2017 [cited by applicant]
JP 2017123427A · 2017 [cited by applicant]
JP 2017195369A · 2017 [cited by applicant]
WO WO2011145635 · 2011 [cited by applicant]
WO WO2016103126 · 2016 [cited by applicant]
WO WO2016189411 · 2016 [cited by applicant]
WO WO2017178912 · 2017 [cited by applicant]
International Search Report (Application No. PCT/IB2019/056307) Dated Oct. 29, 2019. [cited by applicant]
Written Opinion (Application No. PCT/IB2019/056307) Dated Oct. 29, 2019. [cited by applicant]
Chinese Office Action (Application No. 201980050350.X) Dated Dec. 1, 2023. [cited by applicant]