Optimized proximity profile for strained source/drain feature and method of fabricating thereof
View Patent ↗Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.
1. A method comprising:
forming a semiconductor structure that extends from a substrate along a first direction, wherein the semiconductor structure has a height along the first direction and the semiconductor structure extends lengthwise along a second direction that is different than the first direction;
forming a gate structure over a first region of the semiconductor structure, wherein the gate structure extends lengthwise along a third direction that is different than the second direction, the gate structure includes a gate stack and gate spacers, and the gate spacers are disposed along sidewalls of the gate stack;
forming a source/drain trench in a second region of the semiconductor structure by:
performing a first anisotropic etch to provide the source/drain trench with a first depth along the first direction,
performing an isotropic etch that enlarges the source/drain trench along the second direction, wherein the isotropic etch extends the source/drain trench under one of the gate spacers and the isotropic etch implements a fluorine-and-chlorine-containing etch gas, and
performing a second anisotropic etch to extend the source/drain trench to a second depth along the first direction, wherein each of the first anisotropic etch and the second anisotropic etch implement a hydrogen-and-bromine-containing etch gas; and
forming an epitaxial semiconductor structure in the source/drain trench in the second region of the semiconductor structure, wherein the second region is adjacent to the first region.
2. The method of claim 1 , wherein the forming the gate structure includes:
forming the gate stack over the first region of the semiconductor structure;
forming a spacer layer over the gate stack, the first region of the semiconductor structure, and the second region of the semiconductor structure;
performing a first etch and a second etch on the spacer layer to form the gate spacers along the sidewalls of the gate stack; and
wherein the first etch and the second etch begin the forming of the source/drain trench, the first etch provides the source/drain trench with a fourth depth along the first direction that is less than the first depth, the second etch extends the source/drain trench from the fourth depth to a fifth depth along the first direction that is less than the first depth, and the first anisotropic etch extends the source/drain trench from the fifth depth to the first depth.
3. The method of claim 2 , wherein the fourth depth is less than 10% of the height, and the fifth depth is less than 20% of the height.
4. The method of claim 1 , wherein the first depth is about 10% to about 80% of the height and the second depth is about 80% to about 120% of the height.
5. The method of claim 1 , further comprising tuning parameters of the isotropic etch to provide the source/drain trench with a tip under the one of the gate spacers, wherein the one of the gate spacers has a thickness and a tip proximity of the tip is about 50% of the thickness to about 90% of the thickness.
6. The method of claim 1 , wherein:
each of the first anisotropic etch and the second anisotropic etch has a first ratio of vertical etch rate to horizontal etch rate that is about 20 to about 80; and
the isotropic etch has a second ratio of vertical etch rate to horizontal etch rate that is about 1 to about 5.
7. The method of claim 1 , wherein a first duration of the first anisotropic etch is greater than a second duration of and the second anisotropic etch.
8. The method of claim 1 , wherein a first degree of anisotropy of each of the first anisotropic etch and the second anisotropic etch is about 0.95 to about 1 and a second degree of anisotropy of the isotropic etch is about 0.8.
9. The method of claim 1 , wherein the gate stack has a gate height along the first direction, a gate length along the second direction, and a ratio of the gate height to the gate length is greater than about 5.
10. The method of claim 1 , wherein the gate stack is a dummy gate stack, the method further comprising replacing the dummy gate stack with a metal gate stack after forming the epitaxial semiconductor structure in the source/drain trench.
11. A method comprising:
forming a semiconductor structure that extends from a substrate along a first direction, wherein the semiconductor structure has a height along the first direction and the semiconductor structure extends lengthwise along a second direction that is different than the first direction; and
forming a source/drain trench in the semiconductor structure by:
performing a first etch that forms the source/drain trench with a first depth along the first direction in the semiconductor structure, wherein the first etch implements a first fluorine-containing etch gas,
performing a second etch to extend the source/drain trench to a second depth that is greater than the first depth, wherein the second etch implements a second fluorine-containing etch gas,
performing a third etch to extend the source/drain trench to a third depth that is greater than the second depth, wherein the third etch implements a first hydrogen-and-bromine-containing etch gas,
performing a fourth etch to enlarge the source/drain trench along the second direction in the semiconductor structure, wherein the fourth etch implements a third fluorine-containing etch gas, and
performing a fifth etch to extend the source/drain trench to a fourth depth that is greater than the third depth, wherein the fifth etch implements a second hydrogen-and-bromine-containing etch gas and a first duration of the fifth etch is less than a second duration of the third etch; and
forming an epitaxial semiconductor structure in the source/drain trench.
12. The method of claim 11 , wherein the third fluorine-containing etch gas includes chlorine and the second fluorine-containing etch gas includes hydrogen.
13. The method of claim 11 , further comprising tuning parameters of the third etch, the fourth etch, and the fifth etch to provide the source/drain trench with tips having a tip depth that is about 10% of the height to about 40% of the height.
14. The method of claim 11 , further comprising tuning parameters of the third etch, the fourth etch, and the fifth etch to provide the source/drain trench with a proximity footing that is greater than about 8 nm at depths greater than about 80% of the height.
15. The method of claim 11 , wherein the first etch and the second etch remove portions of a dielectric layer to form gate spacers along sidewalls of a gate stack.
16. The method of claim 11 , wherein the forming the epitaxial semiconductor structure in the source/drain trench includes:
forming a first silicon germanium layer that lines and partially fills the source/drain trench, wherein the first silicon germanium layer has a first germanium concentration; and
forming a second silicon germanium layer over the first silicon germanium layer that fills a remainder of the source/drain trench, wherein the second silicon germanium layer has a second germanium concentration that is greater than the first germanium concentration.
17. The method of claim 11 , wherein the forming the epitaxial semiconductor structure in the source/drain trench includes:
forming a first silicon-comprising layer that lines and partially fills the source/drain trench, wherein the first silicon-comprising layer has a first dopant concentration; and
forming a second silicon-comprising layer over the first silicon-comprising layer that fills a remainder of the source/drain trench, wherein the second silicon-comprising layer has a second dopant concentration that is greater than the first dopant concentration.
18. A transistor comprising:
a semiconductor structure extending from a substrate along a first direction, wherein the semiconductor structure has a height along the first direction and the semiconductor structure extends lengthwise along a second direction that is different than the first direction;
a gate structure disposed over a first region of the semiconductor structure, wherein the gate structure extends lengthwise along a third direction, the third direction is different than the second direction, and the gate structure includes a gate stack and gate spacers disposed along sidewalls of the gate stack;
an epitaxial source/drain disposed in a second region of the semiconductor structure, wherein the epitaxial source/drain includes:
a first silicon-comprising layer having a first composition, and
a second silicon-comprising layer having a second composition that is different than the first composition, wherein the second silicon-comprising layer wraps the first silicon-comprising layer;
wherein a tip depth of a tip of the epitaxial source/drain that extends under one of the gate spacers is about 10% of the height to about 40% of the height;
wherein a proximity footing of a bottom portion of the epitaxial source/drain is greater than about 8 nm at depths greater than about 80% of the height; and
wherein the gate stack has a gate height along the first direction, the gate stack has a gate length along the second direction, and a ratio of the gate height to the gate length is greater than about 5.
19. The transistor of claim 18 , wherein:
the first silicon-comprising layer is a first silicon germanium layer having a first germanium concentration; and
the second silicon-comprising layer is a second silicon germanium layer having a second germanium concentration that is less than the first germanium concentration.
20. The transistor of claim 18 , wherein the first silicon-comprising layer is a first silicon layer having a first dopant concentration and the second silicon-comprising layer is a second silicon layer having a second dopant concentration, wherein the second dopant concentration is less than the first dopant concentration.