Analog operation circuit for processing pixel data in analog phase
There is provided a pixel circuit for performing analog operation including a photodiode, a first circuit, a second circuit and an operation circuit. Within a first interval, the photodiode detects first light energy to be stored in the first circuit. Within a second interval, the photodiode detects second light energy to be stored in the second circuit. Within an operation interval, the first circuit outputs a first detection signal according to the first light energy and outputs a second detection signal according to the second light energy for being calculated by the operation circuit.
1. An analog operation circuit, comprising:
a photodiode, configured to generate light energy;
a first circuit, configured to store first light energy generated by the photodiode in a first interval, and output a first detection signal according to the first light energy in an operation interval;
a second circuit, configured to store second light energy generated by the photodiode in a second interval, and output a second detection signal according to the second light energy in the operation interval; and
an absolute difference circuit, coupled to the first circuit and the second circuit, and comprising:
an operation capacitor;
a first input set, configured to control a first charging interval of a first current to charge the operation capacitor according to the first detection signal and an inverted second detection signal in the operation interval when the first light energy is larger than the second light energy; and
a second input set, configured to control a second charging interval of a second current to charge the operation capacitor according to the second detection signal and an inverted first detection signal in the operation interval when the first light energy is smaller than the second light energy.
2. The analog operation circuit as claimed in claim 1 , wherein
the first input set comprises two cascaded transistors respectively configured to receive the first detection signal and the inverted second detection signal, and
the second input set comprises two cascaded transistors respectively configured to receive the second detection signal and the inverted first detection signal.
3. The analog operation circuit as claimed in claim 1 , further comprising a reset transistor configured to reset the first circuit in the first interval and reset the second circuit in the second interval.
4. The analog operation circuit as claimed in claim 1 , further comprising:
a first inverter, coupled between the first circuit and one of the two cascaded transistors of the first input set configured to receive the first detection signal; and
a second inverter, coupled between the second circuit and one of the two cascaded transistors of the second input set configured to receive the second detection signal.
5. The analog operation circuit as claimed in claim 1 , further comprising a transfer transistor configured to
transfer the first light energy from the photodiode to be stored in the first circuit in the first interval, and
transfer the second light energy from the photodiode to be stored in the second circuit in the second interval.
6. The analog operation circuit as claimed in claim 1 , wherein
the first circuit is configured to use a first ramp signal to convert the first light energy to the first detection signal, and
the second circuit is configured to use a second ramp signal to convert the second light energy to the second detection signal, wherein the first ramp signal is in-phase with the second ramp signal.
7. The analog operation circuit as claimed in claim 1 , further comprising an operation reset transistor configured to reset the operation capacitor in the operation interval.
8. An analog operation circuit, comprising:
a photodiode, configured to generate light energy;
a first circuit, configured to store first light energy generated by the photodiode in a first interval, and output a first detection signal according to the first light energy;
a second circuit, configured to store second light energy generated by the photodiode in a second interval, and output a second detection signal according to the second light energy;
an addition circuit, coupled to the first circuit and the second circuit, and comprising:
an operation capacitor configured to store charges of an operation result;
a first operation transistor, configured to control a first charging time of a first current to charge the operation capacitor according to the first detection signal; and
a second operation transistor, configured to control a second charging time of a second current to charge the operation capacitor according to the second detection signal; and
a conversion circuit, coupled to the addition circuit, and configured to convert the charges stored in the operation capacitor into a pulse width signal.
9. The analog operation circuit as claimed in claim 8 , wherein the pulse width signal is coupled to the first operation transistor as the first detection signal or coupled to the second operation transistor as the second detection signal for next operation.
10. The analog operation circuit as claimed in claim 8 , wherein the conversion circuit is coupled the to the addition circuit via a first node, and the conversion circuit comprises:
a first recursive transistor coupled between a voltage source and a second node;
a second recursive transistor coupled between the first node and the second node; and
a third recursive transistor coupled between the second node and a ground voltage.
11. The analog operation circuit as claimed in claim 10 , wherein the second recursive transistor is configured to reset the operation capacitor in an operation reset interval.
12. The analog operation circuit as claimed in claim 10 , wherein the first recursive transistor is configured to receive a ramp signal to convert the charges stored in the operation capacitor into the pulse width signal in a convert interval.
13. The analog operation circuit as claimed in claim 10 , further comprising an inverter coupled downstream of the second node and configured to invert a phase of the pulse width signal.
14. The analog operation circuit as claimed in claim 8 , wherein the analog operation circuit and the conversion circuit form a recursive circuit configured to directly provide the charges stored in the operation capacitor to an identify circuit upon no next operation being required.
15. An analog operation circuit, comprising:
a photodiode, configured to generate light energy;
a first circuit, configured to store first light energy generated by the photodiode in a first interval, and output a first detection signal according to the first light energy;
a second circuit, configured to store second light energy generated by the photodiode in a second interval, and output a second detection signal according to the second light energy;
a subtraction circuit, coupled to the first circuit and the second circuit, and comprising:
an operation capacitor configured to store charges of an operation result;
a first operation transistor, configured to control a charging time of a first current to charge the operation capacitor according to the first detection signal; and
a second operation transistor, configured to control a discharging time of a second current to discharge the operation capacitor according to the second detection signal; and
a conversion circuit, coupled to the subtraction circuit, and configured to convert the charges stored in the operation capacitor into a pulse width signal.
16. The analog operation circuit as claimed in claim 15 , the pulse width signal is coupled to the first operation transistor as the first detection signal or coupled to the second operation transistor as the second detection signal for next operation.
17. The analog operation circuit as claimed in claim 15 , wherein the conversion circuit is coupled the to the subtraction circuit via a first node, and the conversion circuit comprises:
a first recursive transistor coupled between a voltage source and a second node;
a second recursive transistor coupled between the first node and the second node; and
a third recursive transistor coupled between the second node and a ground voltage.
18. The analog operation circuit as claimed in claim 17 , wherein
the second recursive transistor is configured to reset the operation capacitor in an operation reset interval, and
the first recursive transistor is configured to receive a ramp signal to convert the charges stored in the operation capacitor into the pulse width signal in a convert interval.
19. The analog operation circuit as claimed in claim 17 , further comprising an inverter coupled downstream of the second node and configured to invert a phase of the pulse width signal.
20. The analog operation circuit as claimed in claim 15 , wherein the analog operation circuit and the conversion circuit form a recursive circuit configured to directly provide the charges stored in the operation capacitor to an identify circuit upon no next operation being required.