Granted Patent B2

US 12,322,336 · App. 18/293,172 · Granted Jun 3, 2025

Inventors: Wenhui Gao (Beijing, CN); Dan Cao (Beijing, CN); Yonglin Guo (Beijing, CN); Jingwen Zhang (Beijing, CN); Zhiliang Jiang (Beijing, CN)

Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd.; BOE Technology Group Co., Ltd.

G09G3/3233G09G3/32G09G2300/0426G09G2300/0819G09G2300/0852G09G2310/0248G09G2310/061G09G2320/045

Abstract

Claims (67)

1. A pixel driving circuit, comprising:

a driving transistor;

a storage capacitor having a first capacitor electrode and a second capacitor electrode;

a coupling capacitor having a third capacitor electrode and a fourth capacitor electrode;

a control transistor;

a data write transistor having a gate electrode connected to a gate line, a first electrode connected to a data line, and a second electrode connected a first electrode of the control transistor; and

a compensating transistor having a gate electrode connected to a first control signal line; a first electrode connected to the first capacitor electrode, the fourth capacitor electrode, and the second electrode of the control transistor; and a second electrode connected to a first electrode of the driving transistor;

wherein the control transistor has a gate electrode connected to a fourth control signal line, a first electrode connected to the second electrode of the data write transistor, and a second electrode connected to the first capacitor electrode and the fourth capacitor electrode;

a gate electrode of the driving transistor is connected to the third capacitor electrode; and

the control transistor is an n-type transistor;

wherein the compensating transistor is an n-type transistor; and

the first control signal line and the fourth control signal line are connected to a same scan circuit, and are configured to receive output signals of different stages, respectively, from the same scan circuit.

2. The pixel driving circuit of claim 1 , wherein the data write transistor is a p-type transistor.

3. The pixel driving circuit of claim 1 , further comprising a first reset transistor having a gate electrode connected to a first control signal line, a first electrode connected to a first reset signal line, and a second electrode connected to the gate electrode of the driving transistor and the third capacitor electrode.

4. The pixel driving circuit of claim 3 , wherein the first reset transistor is an n-type transistor; and

the first control signal line and the fourth control signal line are connected to a same scan circuit, and are configured to receive output signals of different stages, respectively, from the same scan circuit.

5. The pixel driving circuit of claim 1 , further comprising:

a compensating transistor having a gate electrode connected to a first control signal line; a first electrode connected to the first capacitor electrode, the fourth capacitor electrode, and the second electrode of the control transistor; and a second electrode connected to a first electrode of the driving transistor; and

a first reset transistor having a gate electrode connected to a first control signal line, a first electrode connected to the first reset signal line, and a second electrode connected to the gate electrode of the driving transistor and the third capacitor electrode;

wherein the compensating transistor and the first reset transistor are an n-type transistor; and

the first control signal line and the fourth control signal line are connected to a same scan circuit, and are configured to receive output signals of different stages, respectively, from the same scan circuit.

6. The pixel driving circuit of claim 1 , further comprising a third reset transistor having a gate electrode connected to a third control signal line; a first electrode connected to a third reset signal line; and a second electrode connected to the first electrode of the driving transistor, the second electrode of the light emitting control transistor, and the second electrode of the compensating transistor.

7. The pixel driving circuit of claim 6 , wherein the third control signal line and the gate line are connected to a same scan circuit, and are configured to receive output signals of different stages, respectively, from the same scan circuit.

8. The pixel driving circuit of claim 7 , wherein the third reset transistor and the data write transistor are p-type transistors.

9. A display apparatus, comprising a pixel driving circuit, and one or more scan circuits configured to provide control signals to the pixel driving circuit;

wherein the pixel driving circuit comprises:

a driving transistor;

a storage capacitor having a first capacitor electrode and a second capacitor electrode;

a coupling capacitor having a third capacitor electrode and a fourth capacitor electrode;

a control transistor; and

a data write transistor having a gate electrode connected to a gate line, a first electrode connected to a data line, and a second electrode connected a first electrode of the control transistor;

wherein the control transistor has a gate electrode connected to a fourth control signal line, a first electrode connected to the second electrode of the data write transistor, and a second electrode connected to the first capacitor electrode and the fourth capacitor electrode;

a gate electrode of the driving transistor is connected to the third capacitor electrode; and

the control transistor is an n-type transistor;

wherein the pixel driving circuit further comprises a compensating transistor having a gate electrode connected to a first control signal line; a first electrode connected to the first capacitor electrode, the fourth capacitor electrode, and the second electrode of the control transistor; and a second electrode connected to a first electrode of the driving transistor;

the one or more scan circuits comprise a first scan circuit;

the compensating transistor is an n-type transistor; and

the first control signal line and the fourth control signal line are connected to the first scan circuit, and are configured to receive output signals of different stages, respectively, from the first scan circuit.

10. The display apparatus of claim 9 , wherein the pixel driving circuit further comprises a first reset transistor having a gate electrode connected to a first control signal line, a first electrode connected to a first reset signal line, and a second electrode connected to the gate electrode of the driving transistor and the third capacitor electrode;

the one or more scan circuits comprise a first scan circuit;

the first reset transistor is an n-type transistor; and

the first control signal line and the fourth control signal line are connected to the first scan circuit, and are configured to receive output signals of different stages, respectively, from the first scan circuit.

11. The display apparatus of claim 9 , wherein the pixel driving circuit further comprises:

a compensating transistor having a gate electrode connected to a first control signal line; a first electrode connected to the first capacitor electrode, the fourth capacitor electrode, and the second electrode of the control transistor; and a second electrode connected to a first electrode of the driving transistor; and

a first reset transistor having a gate electrode connected to a first control signal line, a first electrode connected to the first reset signal line, and a second electrode connected to the gate electrode of the driving transistor and the third capacitor electrode;

the one or more scan circuits comprise a first scan circuit;

the compensating transistor and the first reset transistor are an n-type transistor; and

the first control signal line and the fourth control signal line are connected to the first scan circuit, and are configured to receive output signals of different stages, respectively, from the first scan circuit.

12. The display apparatus of claim 9 , wherein the pixel driving circuit further comprises a third reset transistor having a gate electrode connected to a third control signal line; a first electrode connected to a third reset signal line; and a second electrode connected to the first electrode of the driving transistor, the second electrode of the light emitting control transistor, and the second electrode of the compensating transistor;

the one or more scan circuits comprise a second scan circuit; and

the third control signal line and the gate line are connected to a same scan circuit, and are configured to receive output signals of different stages, respectively, from the same scan circuit.

13. A method of operating a pixel driving circuit having a driving transistor; a storage capacitor having a first capacitor electrode and a second capacitor electrode; a coupling capacitor having a third capacitor electrode and a fourth capacitor electrode; a control transistor; and a data write transistor having a gate electrode connected to a gate line, a first electrode connected to a data line, and a second electrode connected a first electrode of the control transistor, wherein the control transistor has a gate electrode connected to a fourth control signal line, a first electrode connected to the second electrode of the data write transistor, and a second electrode connected to the first capacitor electrode and the fourth capacitor electrode; a gate electrode of the driving transistor is connected to the third capacitor electrode; and the control transistor is an n-type transistor;

wherein the method comprises, in a data write phase of a frame of image,

providing a turning on control signal through the gate line to the gate electrode of the data write transistor; and

providing a turning on control signal through the fourth control signal line to the gate electrode of the control transistor;

wherein the pixel driving circuit further comprises a compensating transistor having a gate electrode connected to a first control signal line; a first electrode connected to the first capacitor electrode, the fourth capacitor electrode, and the second electrode of the control transistor; and a second electrode connected to a first electrode of the driving transistor;

the compensating transistor is an n-type transistor; and

the method further comprises providing output signals of different stages from a first scan circuit to the first control signal line and the fourth control signal line, respectively.

14. The method of claim 13 , wherein the pixel driving circuit further comprises a first reset transistor having a gate electrode connected to a first control signal line, a first electrode connected to a first reset signal line, and a second electrode connected to the gate electrode of the driving transistor and the third capacitor electrode; and

the method further comprises providing output signals of different stages from a first scan circuit to the first control signal line and the fourth control signal line, respectively.

15. The method of claim 13 , wherein the pixel driving circuit further comprises:

a compensating transistor having a gate electrode connected to a first control signal line; a first electrode connected to the first capacitor electrode, the fourth capacitor electrode, and the second electrode of the control transistor; and a second electrode connected to a first electrode of the driving transistor; and

a first reset transistor having a gate electrode connected to a first control signal line, a first electrode connected to the first reset signal line, and a second electrode connected to the gate electrode of the driving transistor and the third capacitor electrode;

wherein the compensating transistor and the first reset transistor are an n-type transistor; and

the method further comprises providing output signals of different stages from a first scan circuit to the first control signal line and the fourth control signal line, respectively.

16. The method of claim 13 , wherein the pixel driving circuit further comprises a third reset transistor having a gate electrode connected to a third control signal line; a first electrode connected to a third reset signal line; and a second electrode connected to the first electrode of the driving transistor, the second electrode of the light emitting control transistor, and the second electrode of the compensating transistor; and

the method further comprises providing output signals of different stages from a second scan circuit to the third control signal line and the gate line, respectively.

Assignments (1)

Continuity (1)

References Cited (31)