IP Library Granted Patent US 12,322,704
Granted Patent B2
US 12,322,704 · App. 18/359,924 · Granted Jun 3, 2025

Package structure with underfill

Inventors: Yu-Sheng Lin (Zhubei, TW); Shin-Puu Jeng (Hsinchu, TW); Po-Yao Lin (Zhudong Township, Hsinchu County, TW); Chin-Hua Wang (New Taipei, TW); Shu-Shen Yeh (Taoyuan, TW); Che-Chia Yang (Taipei, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L23/5385H01L21/4853H01L21/4857H01L21/6835H01L23/13H01L23/5383H01L23/5386H01L2221/68372
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Quick Facts
Patent No.
US 12,322,704
App. No.
18/359,924
Granted
Jun 3, 2025
Kind
B2
Abstract

A package structure is provided. The package structure includes a substrate having interior sidewalls forming a recess. The interior sidewalls have an upper sidewall, a lower sidewall, and an intermediate sidewall. The intermediate sidewall is between the upper sidewall and the lower sidewall. The upper sidewall, the lower sidewall, and the intermediate sidewall have different slopes. The package structure also includes a chip-containing structure over the substrate. A component of the chip-containing structure is partially or completely surrounded by the interior sidewalls.

Claims (29)

1. A package structure, comprising:

a substrate having interior sidewalls forming a recess, wherein the interior sidewalls have an upper sidewall, a lower sidewall, and an intermediate sidewall, the intermediate sidewall is between the upper sidewall and the lower sidewall, and the upper sidewall, the lower sidewall, and the intermediate sidewall have different slopes; and

a chip-containing structure over the substrate, wherein a component of the chip-containing structure is at least partially surrounded by the interior sidewalls, the chip-containing structure has a redistribution structure and a chip structure, the component and the chip structure are disposed over opposite surfaces of the redistribution structure, and the redistribution structure has a plurality of polymer-containing layers and a plurality of conductive features.

2. The package structure as claimed in claim 1 , wherein the chip-containing structure further has a second chip structure laterally spaced apart from the chip structure, the component extends across opposite sidewalls of the chip structure and the second chip structure, and the chip structure and the second chip structure together extend across opposite sidewalls of the component.

3. The package structure as claimed in claim 2 , wherein the component is an interconnection chip, and the interconnection chip forms electrical connections between the first chip structure and the second chip structure.

4. The package structure as claimed in claim 3 , wherein the component has no active device.

5. The package structure as claimed in claim 1 , wherein the lower sidewall is steeper than the intermediate sidewall.

6. The package structure as claimed in claim 5 , wherein the intermediate sidewall is steeper than the upper sidewall.

7. The package structure as claimed in claim 1 , further comprising:

an underfill structure filling the recess.

8. The package structure as claimed in claim 7 , further comprising:

a plurality of tin-containing bonding structures between the substrate and the chip-containing structure, wherein the underfill structure laterally surrounds the tin-containing bonding structures.

9. The package structure as claimed in claim 1 , wherein the upper sidewall is at a first angle to the vertical, the lower sidewall is at a second angle to the vertical, the first angle is in a range from about 30 degrees to about 60 degrees, and a ratio of the first angle to the second angle is in a range from about 2 to about 4.

10. The package structure as claimed in claim 1 , wherein the intermediate sidewall is steeper than the upper sidewall, the lower sidewall is steeper than the intermediate sidewall, and the intermediate sidewall is in direct contact with the upper sidewall and the lower sidewall.

11. A package structure, comprising:

a substrate having interior sidewalls forming a recess, wherein the interior sidewalls have an upper sidewall, a lower sidewall, and an intermediate sidewall, and the intermediate sidewall is between the upper sidewall and the lower sidewall, wherein the substrate has a first surface and a second surface opposite to the first surface, the recess extends from the first surface towards the second surface, and the upper sidewall is between the intermediate sidewall and the first surface, wherein the upper sidewall is at a first acute angle to a vertical substantially perpendicular to the second surface, the intermediate sidewall is at a second acute angle to the vertical, the lower sidewall is at a third acute angle to the vertical, the first acute angle is larger than the second acute angle, and the second acute angle is larger than the third acute angle; and

a chip-containing structure over the substrate, wherein a component of the chip-containing structure enters the recess.

12. The package structure as claimed in claim 11 , wherein the chip-containing structure has a second component entering the recess.

13. The package structure as claimed in claim 12 , wherein the chip-containing structure has a first chip structure and a second chip structure laterally spaced apart from the first chip structure, the component extends across opposite sidewalls of the first chip structure and the second chip structure, and the second component extends across the opposite sidewalls of the first chip structure and the second chip structure.

14. The package structure as claimed in claim 13 , wherein the chip-containing structure has a redistribution structure, the component and the first chip are disposed over opposite surfaces of the redistribution structure, the second component and the second chip structure are disposed over the opposite surfaces of the redistribution structure, and the redistribution structure has a plurality of insulating layers and a plurality of conductive features.

15. The package structure as claimed in claim 11 , wherein the chip-containing structure extends across outermost edges of the recess.

16. A package structure, comprising:

a substrate having a recess, wherein the recess has an upper sidewall, a lower sidewall, and an intermediate sidewall, the intermediate sidewall is between the upper sidewall and the lower sidewall, and the lower sidewall is steeper than the upper sidewall;

a chip-containing structure over the substrate, wherein a component of the chip-containing structure enters the recess, wherein the chip-containing structure extends across outermost edges of the recess; and

an underfill structure overfilling the recess and covering an entirety of a bottom surface of the component.

17. The package structure as claimed in claim 16 , wherein the intermediate sidewall and the lower sidewall have different slopes.

18. The package structure as claimed in claim 16 , wherein the chip-containing structure has a first chip structure and a second chip structure laterally spaced apart from the first chip structure, the component extends across opposite sidewalls of the first chip structure and the second chip structure.

19. The package structure as claimed in claim 18 , wherein the chip-containing structure has a second component extending across the opposite sidewalls of the first chip structure and the second chip structure.

20. The package structure as claimed in claim 19 , wherein the chip-containing structure has a redistribution structure, the component and the first chip are disposed over opposite surfaces of the redistribution structure, the second component and the second chip structure are disposed over the opposite surfaces of the redistribution structure, and the redistribution structure has a plurality of insulating layers and a plurality of conductive features.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2023
From: LIN, YU-SHENG; JENG, SHIN-PUU; LIN, PO-YAO; WANG, CHIN-HUA; YEH, SHU-SHEN; YANG, CHE-CHIA
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 064397/0727 →
Continuity (2)
Continuation 17459215 · Aug 27, 2021
Related Publication 20240021529A1 · Jan 18, 2024
References Cited (47)
US 5607883A · Bhattacharyya et al. · 1997 [cited by applicant]
US 6861363B2 · Harchanko et al. · 2005 [cited by applicant]
US 6953891B2 · Bolken · 2005 [cited by examiner]
US 7893527B2 · Shin et al. · 2011 [cited by applicant]
US 7977579B2 · Bathan · 2011 [cited by examiner]
US 7989838B2 · Ku · 2011 [cited by examiner]
US 8115296B2 · Bolken · 2012 [cited by examiner]
US 8227821B2 · Bogner · 2012 [cited by examiner]
US 8352496B2 · Johnston · 2013 [cited by examiner]
US 8536695B2 · Liu et al. · 2013 [cited by applicant]
US 8587009B2 · Tsang · 2013 [cited by examiner]
US 8624268B2 · Cho · 2014 [cited by examiner]
US 8922000B2 · Han · 2014 [cited by applicant]
US 8952501B2 · Huang et al. · 2015 [cited by applicant]
US 8993380B2 · Hou et al. · 2015 [cited by applicant]
US 8994048B2 · Choi · 2015 [cited by examiner]
US 9000584B2 · Lin et al. · 2015 [cited by applicant]
US 9048222B2 · Hung et al. · 2015 [cited by applicant]
US 9048233B2 · Wu et al. · 2015 [cited by applicant]
US 9064879B2 · Hung et al. · 2015 [cited by applicant]
US 9082743B2 · Hung et al. · 2015 [cited by applicant]
US 9111949B2 · Yu et al. · 2015 [cited by applicant]
US 9263511B2 · Yu et al. · 2016 [cited by applicant]
US 9281254B2 · Yu et al. · 2016 [cited by applicant]
US 9299649B2 · Chiu et al. · 2016 [cited by applicant]
US 9331006B2 · Nakao et al. · 2016 [cited by applicant]
US 9337116B2 · Pagaila et al. · 2016 [cited by applicant]
US 9362190B2 · Shioji · 2016 [cited by examiner]
US 9368460B2 · Yu et al. · 2016 [cited by applicant]
US 9372206B2 · Wu et al. · 2016 [cited by applicant]
US 9425126B2 · Kuo et al. · 2016 [cited by applicant]
US 9443783B2 · Lin et al. · 2016 [cited by applicant]
US 9461018B1 · Tsai et al. · 2016 [cited by applicant]
US 9496189B2 · Yu et al. · 2016 [cited by applicant]
US 9559028B2 · Takeda et al. · 2017 [cited by applicant]
US 9595640B2 · Bae et al. · 2017 [cited by applicant]
US 9666502B2 · Chen et al. · 2017 [cited by applicant]
US 9704840B2 · Nishimura et al. · 2017 [cited by applicant]
US 9735131B2 · Su et al. · 2017 [cited by applicant]
US 10418329B2 · Li · 2019 [cited by examiner]
US 11373972B2 · Karhade · 2022 [cited by examiner]
US 11594491B2 · Weng · 2023 [cited by examiner]
US 11784130B2 · Lin · 2023 [cited by examiner]
US 20140175067A1 · Reichenbach et al. · 2014 [cited by applicant]
US 20180211926A1 · Jang et al. · 2018 [cited by applicant]
TW 201336121A · 2013 [cited by applicant]
Chinese language office action dated Jan. 30, 2023, issued in application No. TW 111103063. [cited by applicant]