IP Library › Granted Patent US 12,324,137
Granted Patent B2
US 12,324,137 · App. 18/315,728 · Granted Jun 3, 2025

Circuit board enclosure with composite liner for inhibiting electrostatic discharge

Inventor: Ching-Jen Chen (Taoyuan, TW)
Assignee: QUANTA COMPUTER INC.
H05K9/0067G06F1/1658
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,324,137
App. No.
18/315,728
Granted
Jun 3, 2025
Kind
B2
Abstract

A computing device for inhibiting electrostatic discharge (ESD) in a computing system, the computing device including a mainboard with computing circuitry for the computing system, a tray in which the mainboard is affixed, and a composite liner for absorbing high-frequency energy and electromagnetic interference from the ESD. The composite liner includes a high-frequency energy absorption layer and an insulation layer coupled to a first surface of the high-frequency energy absorption layer. The high-frequency energy absorption layer includes a high-frequency energy absorption material, and the insulation layer includes an electrical-insulating material. A circuit board enclosure includes the composite liner and a panel with the composite liner at least partially lining an internal receiving surface of the panel. A circuit board is positioned inside the circuit board enclosure with the composite liner interposed between the circuit board and the panel to protect the electronic component from ESD.

Claims (34)

1. A computing device for inhibiting electrostatic discharge (ESD) in a computing system, the computing device comprising:

a mainboard with computing circuitry for the computing system;

a tray in which the mainboard is affixed, the tray having an internal receiving surface; and

a composite liner for absorbing high-frequency energy and electromagnetic interference from the ESD, the composite liner being positioned in the tray between the mainboard and the internal receiving surface, the composite liner including

a high-frequency energy absorption layer including a high-frequency energy absorption material, the high-frequency energy absorption layer having a first surface; and

a first insulation layer including a first electrical-insulating material, the first insulation layer being coupled to the first surface of the high-frequency energy absorption layer.

2. The computing device of claim 1 , wherein the high-frequency energy absorption material includes a silicone gel containing magnetic particles of metal oxide and thermoconductive filler.

3. The computing device of claim 1 , wherein the composite liner further includes a second insulation layer including a second electrical-insulating material, the second insulation layer being coupled to a second surface of the high-frequency energy absorption layer opposite the first surface of the high-frequency energy absorption layer.

4. The computing device of claim 3 , wherein the first electrical-insulating material includes at least one of biaxially-oriented polyethylene terephthalate (Mylar), a polymide material, and a polyester material.

5. The computing device of claim 1 , wherein the first insulation layer is adhesively coupled to the first surface of the high-frequency energy absorption layer.

6. The computing device of claim 1 , wherein the first insulation layer covers substantially all of the internal receiving surface of the tray.

7. The computing device of claim 6 , wherein the high-frequency energy absorption layer covers a region of the tray corresponding to location of an electronic component of the mainboard.

8. The computing device of claim 1 , wherein the high-frequency energy absorption layer absorbs high-frequency energy from ESD entering through an aperture in the tray.

9. A circuit board enclosure for inhibiting ESD in a computing system, the circuit board enclosure comprising:

a tray adapted for receiving a mainboard with computing circuitry for the computing system, the tray having an internal receiving surface; and

a composite liner for absorbing high-frequency energy and electromagnetic interference from the ESD, the composite liner at least partially covering the internal receiving surface of the tray, the composite liner including

a high-frequency energy absorption layer including a high-frequency energy absorption material, the high-frequency energy absorption layer having a first surface; and

a first insulation layer including a first electrical-insulating material, the first insulation layer being coupled to the first surface of the high-frequency energy absorption layer.

10. The circuit board enclosure of claim 9 , wherein the high-frequency energy absorption material includes a silicone gel containing magnetic particles of metal oxide and thermoconductive filler.

11. The circuit board enclosure of claim 9 , wherein the composite liner further includes a second insulation layer including a second electrical-insulating material, the second insulation layer being coupled to a second side of the high-frequency energy absorption layer, the second side being opposite the first side of the high-frequency energy absorption layer.

12. The circuit board enclosure of claim 9 , wherein the first electrical-insulating material include at least one of biaxially-oriented polyethylene terephthalate (Mylar), a polymide material, and a polyester material.

13. The circuit board enclosure of claim 9 , wherein the first insulation layer is adhesively coupled to the first side of the high-frequency energy absorption layer.

14. The circuit board enclosure of claim 9 , wherein the first insulation layer covers substantially all of the internal receiving surface of the tray.

15. The circuit board enclosure of claim 9 , wherein the high-frequency energy absorption layer covers a region of the tray corresponding to a predetermined location for placing an electronic component of the mainboard.

16. A composite liner for inhibiting ESD in a computing system, the composite liner comprising:

a high-frequency energy absorption layer including a high-frequency energy absorption material, the high-frequency energy absorption layer having a first surface and a second surface opposite the first surface;

a first insulation layer including a first electrical-insulating material, the first insulation layer being coupled to the first surface of the high-frequency energy absorption layer; and

a second insulation layer including a second electrical-insulating material, the second insulation layer being coupled to the second surface of the high-frequency energy absorption layer.

17. The electronic system of claim 16 , wherein the high-frequency energy absorption material includes a silicone gel containing magnetic particles of metal oxide and thermoconductive filler.

18. The composite liner of claim 16 , wherein the first electrical-insulating material and the second electrical-insulating material each include at least one of biaxially-oriented polyethylene terephthalate (Mylar), a polymide material, and a polyester material.

19. The composite liner of claim 16 further comprising:

a first bonding layer bonding the first side of the high-frequency energy absorption layer with the first insulation layer; and

a second bonding layer bonding the second side of the high-frequency energy absorption layer with the second insulation layer.

20. The composite liner of claim 16 , wherein at least one of the first electrical-insulating material and the second electrical-insulating material has flame-retardant property.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2023
From: CHEN, CHING-JEN
To: QUANTA COMPUTER INC.
Reel/Frame 063630/0674 →
Continuity (1)
Related Publication 20240381599A1 · Nov 14, 2024
References Cited (34)
US 3645281A · Seidler · 1972 [cited by examiner]
US 4139097A · Bowman · 1979 [cited by examiner]
US 4160503A · Ohlbach · 1979 [cited by examiner]
US 4211324A · Ohlbach · 1980 [cited by examiner]
US 4241829A · Hardy · 1980 [cited by examiner]
US 4293070A · Ohlbach · 1981 [cited by examiner]
US 4404615A · Dep · 1983 [cited by examiner]
US 4480747A · Kazor · 1984 [cited by examiner]
US 4565288A · Walther · 1986 [cited by examiner]
US 4709297A · Walther · 1987 [cited by examiner]
US 4767003A · Rice · 1988 [cited by examiner]
US 4926007A · Aufderheide · 1990 [cited by examiner]
US 5017260A · Bardford · 1991 [cited by examiner]
US 5133452A · Ohashi · 1992 [cited by examiner]
US 5232091A · Hennessy · 1993 [cited by examiner]
US 5263583A · Ohashi · 1993 [cited by examiner]
US 5348150A · Brenner · 1994 [cited by examiner]
US 5361901A · Schenz · 1994 [cited by examiner]
US 5808358A · Vinciarelli · 1998 [cited by examiner]
US 5979660A · Pakeriasamy · 1999 [cited by examiner]
US 6132607A · Chen · 2000 [cited by examiner]
US 6981585B2 · Kitamura · 2006 [cited by examiner]
US 6989196B2 · Chatterjee · 2006 [cited by examiner]
US 7223922B2 · Bandy, IV · 2007 [cited by examiner]
US 7310239B1 · Fjelstad · 2007 [cited by examiner]
US 8455070B2 · Nagai · 2013 [cited by examiner]
US 11335649B2 · Wang · 2022 [cited by examiner]
US 11576287B2 · Lee · 2023 [cited by examiner]
US 11974420B2 · Lee · 2024 [cited by examiner]
US 20030146529A1 · Chen · 2003 [cited by examiner]
US 20110194225A1 · Onishi et al. · 2011 [cited by applicant]
TW 200939944A · 2009 [cited by applicant]
TW Office Action for Application No. 112126193 mailed May 23, 2024, w/ First Office Action Summary, 7 pp. [cited by applicant]
TW Search Report for Application No. 112126193 mailed May 23, 2024, w/ First Office Action, 1 p. [cited by applicant]