IP Library › Granted Patent US 12,324,233
Granted Patent B2
US 12,324,233 · App. 17/219,083 · Granted Jun 3, 2025

Semiconductor device

Inventors: Su Young Bae (Daegu, KR); Jong Ho Park (Suwon-si, KR); Dong Soo Lee (Gunpo-si, KR); Wan Don Kim (Seongnam-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10D84/85H10D84/0179H10D84/0181H10D84/038
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Quick Facts
Patent No.
US 12,324,233
App. No.
17/219,083
Granted
Jun 3, 2025
Kind
B2
Abstract

A semiconductor device includes first and second active patterns disposed on a substrate, a field insulating film disposed between the first and second active patterns, a first gate structure intersecting the first active pattern, and a second gate structure intersecting the second active pattern, in which the first gate structure includes a first gate insulating film on the first active pattern, a first upper insertion film on the first gate insulating film, and a first upper conductive film on the first upper insertion film, and the second gate structure includes a second gate insulating film on the second active pattern, a second upper insertion film on the second gate insulating film, and a second upper conductive film on the second upper insertion film. Each of the first and second upper insertion films may include an aluminum nitride film. Each of the first and second upper conductive films may include aluminum.

Claims (62)

1. A semiconductor device comprising:

a first active pattern and a second active pattern disposed on a substrate and being adjacent to each other;

a field insulating film disposed on the substrate, between the first active pattern and the second active pattern, and being in direct contact with the first active pattern and the second active pattern;

a first gate structure intersecting the first active pattern, on the substrate; and

a second gate structure intersecting the second active pattern, on the substrate,

wherein

the first gate structure includes a first gate insulating film, which is on the first active pattern, a first upper insertion film, which is on the first gate insulating film, and a first upper conductive film, which is on the first upper insertion film and in contact with the first upper insertion film,

the second gate structure includes a second gate insulating film, which is on the second active pattern, a second upper insertion film, which is on the second gate insulating film, and a second upper conductive film, which is on the second upper insertion film and in contact with the second upper insertion film,

each of the first upper insertion film and the second upper insertion film is an aluminum nitride film,

each of the first upper conductive film and the second upper conductive film includes aluminum,

the first upper insertion film is not in contact with the first gate insulating film,

the first upper conductive film is over the first upper insertion film, but not interposed between two adjacent separate portions of the first upper insertion film,

the second upper conductive film is over the second upper insertion film, and interposed between two adjacent separate portions of the second upper insertion film,

the second upper insertion film is in direct contact with the second gate insulating film,

the first gate structure further includes a lower insertion film and a lower conductive film, with the aluminum nitride film of the first upper insertion film disposed between the lower insertion film and the first upper conductive film and spaced apart from the lower insertion film on the first active pattern, the lower conductive film directly contacting the first upper insertion film and the lower insertion film, and the lower insertion film including a nitride or an oxide of a metal having an electronegativity of about 1.5 or higher,

the first active pattern is disposed in a p-type metal-oxide semiconductor (PMOS) region, and

the second active pattern is disposed in an n-type metal-oxide semiconductor (NMOS) region.

2. The semiconductor device of claim 1 , wherein the lower conductive film is disposed between the first upper insertion film and the first gate insulating film.

3. The semiconductor device of claim 1 , wherein

the lower insertion film is disposed between the first gate insulating film and the first upper insertion film.

4. The semiconductor device of claim 3 , wherein the lower insertion film includes at least one of molybdenum oxide, molybdenum nitride, niobium oxide, niobium nitride, nickel oxide, tin oxide, or titanium oxide.

5. The semiconductor device of claim 3 , wherein the lower insertion film is not formed on the second active pattern.

6. The semiconductor device of claim 1 , wherein

the first upper insertion film and the second upper insertion film are in direct contact with each other, and

the first upper conductive film and the second upper conductive film are in direct contact with each other.

7. The semiconductor device of claim 6 , wherein

the lower insertion film and the lower conductive film are disposed between the first gate insulating film and the first upper insertion film, and

an end portion of the lower insertion film and an end portion of the lower conductive film are disposed on a top surface of the field insulating film.

8. The semiconductor device of claim 1 , wherein each of the first active pattern and the second active pattern includes a lower pattern, which protrudes from the substrate, and sheet patterns, which are spaced apart from the lower pattern.

9. A semiconductor device comprising:

a first active pattern and a second active pattern disposed on a substrate and being adjacent to each other;

a field insulating film disposed on the substrate, between the first active pattern and the second active pattern, and being in direct contact with the first active pattern and the second active pattern; and

a gate structure intersecting the first active pattern and the second active pattern, on the field insulating film,

wherein

the gate structure includes a gate insulating film, which is disposed on the first active pattern and the second active pattern, a lower conductive film, which is disposed on part of the gate insulating film on the first active pattern and defines a stair on a top surface of the field insulating film, an aluminum nitride film, which is disposed on the lower conductive film, across the first active pattern and the second active pattern, and an upper conductive film, which is disposed on the aluminum nitride film, across the first active pattern and the second active pattern, and includes aluminum,

the gate structure further includes a lower insertion film on the first active pattern, with the aluminum nitride film disposed between the lower insertion film and the upper conductive film and spaced apart from the lower insertion film on the first active pattern, the lower conductive film directly contacting the aluminum nitride film and the lower insertion film, and the lower insertion film including a nitride or an oxide of a metal having an electronegativity of about 1.5 or higher,

the upper conductive film is over the aluminum nitride film, but not interposed between two adjacent separate portions of the aluminum nitride film on the first active pattern,

the upper conductive film is over the aluminum nitride film, and interposed between two adjacent separate portions of the aluminum nitride film on the second active pattern,

the aluminum nitride film is in direct contact with the gate insulating film, on the second active pattern,

the first active pattern is disposed in a p-type metal-oxide semiconductor (PMOS) region, and

the second active pattern is disposed in an n-type metal-oxide semiconductor (NMOS) region.

10. The semiconductor device of claim 9 , wherein

the lower insertion film is in contact with the gate insulating film, and interposed between the lower conductive film and the gate insulating film.

11. The semiconductor device of claim 10 , wherein an end portion of the lower insertion film is disposed on the top surface of the field insulating film.

12. A semiconductor device comprising:

a first active pattern disposed on a substrate, the first active pattern including a first lower pattern and first sheet patterns, which are separated from the first lower pattern;

a second active pattern disposed on the substrate, the second active pattern including a second lower pattern, which is adjacent to the first lower pattern, and second sheet patterns, which are separated from the second lower pattern;

a field insulating film disposed between, and in direct contact with, the first active pattern and the second active pattern; and

a gate structure surrounding the first sheet patterns and the second sheet patterns, on the field insulating film,

wherein

the gate structure includes a gate insulating film, which surrounds the first sheet patterns and the second sheet patterns, a lower conductive film, which is on the gate insulating film, an aluminum nitride film, which is on the lower conductive film, and an upper conductive film, which is on the aluminum nitride film,

the gate structure further includes a lower insertion film on the first active pattern, with the aluminum nitride film disposed between the lower insertion film and the upper conductive film and spaced apart from the lower insertion film on the first active pattern, the lower conductive film directly contacting the aluminum nitride film and the lower insertion film, and the lower insertion film including a nitride or an oxide of a metal having an electronegativity of about 1.5 or higher,

the lower conductive film surrounds the first sheet patterns, and is not formed along circumferences of the second sheet patterns,

the aluminum nitride film is in contact with the gate insulating film surrounding the second sheet patterns,

the upper conductive film is over the first sheet patterns, but not interposed between two adjacent ones of the first sheet patterns,

the upper conductive film is over the second sheet patterns, and interposed between two adjacent ones of the second sheet patterns,

the first active pattern is disposed in a p-type metal-oxide semiconductor (PMOS) region, and

the second active pattern is disposed in an n-type metal-oxide semiconductor (NMOS) region.

13. The semiconductor device of claim 12 , wherein the aluminum nitride film is not formed in spaces between the first lower pattern and the first sheet patterns.

14. The semiconductor device of claim 12 , wherein the lower insertion film is disposed between the gate insulating film and the lower conductive film, along circumferences of the first sheet patterns, and

the lower insertion film is not formed along the circumferences of the second sheet patterns.

15. The semiconductor device of claim 14 , wherein the lower insertion film includes at least one of molybdenum oxide, molybdenum nitride, niobium oxide, niobium nitride, nickel oxide, tin oxide, or titanium oxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2021
From: BAE, SU YOUNG; PARK, JONG HO; LEE, DONG SOO; KIM, WAN DON
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 055786/0091 →
Priority Claims (1)
KR 10-2020-0105130 · Aug 21, 2020 · national
Continuity (1)
Related Publication 20220059533A1 · Feb 24, 2022
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