3D 1T1C stacked dram structure and method to fabricate
Embodiments disclosed herein include three-dimensional 3D arrays of memory cells and methods of forming such devices. In an embodiment a memory device comprises, a substrate surface, and a three-dimensional (3D) array of memory cells over the substrate surface. In an embodiment each memory cell comprises a transistor and a capacitor. In an embodiment the transistor of each memory cell comprises, a semiconductor channel, with a first end of the semiconductor channel electrically coupled to a bit line that runs substantially parallel to the substrate surface, and a second end of the semiconductor channel is electrically coupled to the capacitor. The transistor may also comprise a gate dielectric on a surface of the semiconductor channel between the first end and the second end of the semiconductor channel. In an embodiment, the gate dielectric is contacted by a word line that runs substantially perpendicular to the substrate surface.
1. A method of forming a memory device, comprising:
forming a stack comprising a plurality of conductive layers alternating with first insulating layers;
patterning the stack, wherein each conductive layer is patterned to form a bit line and an array of memory cell regions, each memory cell region comprising:
a transistor region having a sacrificial channel formed of the conductive layer; and
a capacitor region having a capacitor electrode formed of the conductive layer and connected to the sacrificial channel;
forming spacers along sidewalls of the bit lines;
disposing a second insulating layer over the patterned stack and the spacers;
forming first trenches through the second insulating layer to expose the transistor regions;
removing the sacrificial channel with an etching process to form a cavity;
disposing a semiconductor channel in the cavity;
disposing a gate dielectric over the semiconductor channel;
filling the first trenches with a conductive material to form a plurality of word lines;
forming second trenches through the second insulating layer to expose the capacitor regions;
disposing a capacitor dielectric over the exposed capacitor electrodes; and
filling the second trenches with a conductive material.
2. The method of claim 1 , wherein four or more memory cell regions are patterned into each conductive layer.
3. The method of claim 1 , wherein the plurality of conductive layers in the stack comprises eight or more layers.
4. The method of claim 1 , wherein the stack is positioned in back end metal layers of a die.
5. A method of fabricating a memory device, the method comprising:
forming a three-dimensional (3D) array of memory cells over a substrate surface, wherein each memory cell comprises a transistor and a capacitor, the transistor comprising a semiconductor channel laterally adjacent to the capacitor in a plane parallel with the substrate surface, wherein a bit line runs substantially parallel to the substrate surface and couples memory cells along a length of the bit line and across a width of the bit line, and wherein forming the transistor of each memory cell comprises:
forming the semiconductor channel, wherein a first end of the semiconductor channel is electrically coupled to the bit line, wherein the bit line is in the plane parallel with the surface substrate, and a second end of the semiconductor channel is electrically coupled to the capacitor; and
forming a gate dielectric on a surface of the semiconductor channel between the first end and the second end of the semiconductor channel, wherein the gate dielectric is contacted by a word line that runs substantially perpendicular to the substrate surface.
6. The method of claim 5 , further comprising:
forming a plurality of bit lines in a stack, wherein the bit lines are separated by insulating layers.
7. The method of claim 6 , wherein the plurality of bit lines comprises eight or more bit lines.
8. The method of claim 6 , wherein each bit line is electrically coupled to two or more semiconductor channels.
9. The method of claim 6 , further comprising:
forming a spacer along sidewall surfaces of the plurality of bit lines.
10. The method of claim 6 , wherein the plurality of bit lines terminate in a stair step pattern.
11. The method of claim 5 , wherein the semiconductor channels are thin-film semiconductor channels.
12. The method of claim 5 , wherein forming each capacitor comprises:
forming a capacitor electrode electrically coupled to the second end of the semiconductor channel;
forming a capacitor dielectric over the capacitor electrode; and
forming a drain electrode.
13. The method of claim 12 , wherein the capacitor electrode and the drain electrode have interdigitated surfaces.
14. The method of claim 12 , wherein a plurality of capacitors share the same drain electrode.
15. The method of claim 14 , wherein the drain electrode extends in a direction parallel to the word line.
16. The method of claim 12 , wherein the capacitor electrodes have a thickness that is equal to a thickness of the bit line.
17. A method of fabricating an electronic system, the method comprising:
providing a motherboard;
coupling a die to the motherboard, wherein the die comprises:
a substrate surface; and
a three-dimensional (3D) array of memory cells over the substrate surface, wherein each memory cell comprises a transistor and a capacitor, wherein the transistor comprises a semiconductor channel laterally adjacent to the capacitor in a plane that is substantially parallel to the substrate surface, wherein a bit line runs substantially parallel to the substrate surface and couples memory cells along a length of the bit line and across a width of the bit line, and wherein the transistor of each memory cell comprises:
the semiconductor channel, wherein a first end of the semiconductor channel is electrically coupled to the bit line, wherein the bit line is in the plane parallel with the surface substrate, and a second end of the semiconductor channel is electrically coupled to the capacitor; and
a gate dielectric on a surface of the semiconductor channel between the first end and the second end of the semiconductor channel, wherein the gate dielectric is contacted by a word line that runs substantially perpendicular to the substrate; and
wherein the capacitor of each memory cell comprises:
a capacitor electrode electrically coupled to the second end of the semiconductor channel;
a capacitor dielectric over the capacitor electrode; and
a drain electrode.
18. The method of claim 17 , wherein the 3D array of memory cells is positioned in a back end metal layer of the die.