Granted Patent B2

US 12,332,385 · App. 17/329,816 · Granted Jun 17, 2025

Inventor: Koichi Hasegawa (Kanagawa, JP)

Assignee: Sony Semiconductor Solutions Corporation

G01S7/4865G01S7/4863G01S17/89H10F30/225

Abstract

Claims (35)

1. A light detecting device comprising:

a plurality of pixels arranged in an array, the plurality of pixels including a first pixel and a second pixel,

wherein the first pixel includes a first avalanche diode, a first inverter, and a first logic circuit,

wherein a first input node of the first logic circuit is configured to receive a second output based on a first output the first inverter,

wherein the second pixel includes a second avalanche diode, a second inverter, and a second logic circuit,

wherein a first input node of the second logic circuit is configured to receive a fourth output based on a third output of the second inverter,

wherein a second input node of the second logic circuit is coupled to an output node of the first logic circuit, and

wherein the first pixel and the second pixel are disposed in a first row of the array.

2. The light detecting device of claim 1 , wherein the first logic circuit and the second logic circuit are each an OR circuit.

3. The light detecting device of claim 1 , wherein the first pixel further includes a first AND circuit, and wherein a first input node of the first AND circuit is coupled to an output node of the first inverter.

4. The light detecting device of claim 3 , wherein the first logic circuit is configured to receive a sixth output based on a fifth output of the first AND circuit.

5. The light detecting device of claim 1 , wherein the first avalanche diode and the second avalanche diode are in a first substrate, and wherein the first inverter and the second inverter are in a second substrate that is stacked on the first substrate.

6. The light detecting device of claim 5 , wherein a time measurement section is disposed in the second substrate.

7. The light detecting device of claim 1 , wherein a second input node of the first logic circuit is coupled to a controller.

8. The light detecting device of claim 1 , wherein the first pixel and the second pixel are adjacent to each other.

9. A light detecting device comprising:

a plurality of pixels arranged in an array, the plurality of pixels including a first pixel, a second pixel, and a third pixel,

wherein the first pixel of the plurality of pixels includes a first avalanche diode, a first inverter, and a first logic circuit,

wherein a first input node of the first logic circuit is configured to receive a second output based on a first output of the first inverter;

wherein the second pixel of the plurality of pixels includes a second avalanche diode, a second inverter, and a second logic circuit,

wherein a first input node of the second logic circuit is configured to receive a fourth output based on a third output of the second inverter,

wherein the second input node of the second logic circuit is coupled to an output node of the first logic circuit,

wherein the third pixel includes a third avalanche diode, a third inverter, and a third logic circuit,

wherein a first input node of the third logic circuit is configured to receive a sixth output based on a fifth output of the third inverter,

wherein the second input node of the third logic circuit is coupled to an output node of the second logic circuit,

wherein the first pixel, the second pixel, and the third pixel are disposed in a first row of the array.

10. The light detecting device of claim 9 , wherein the first logic circuit, the second logic circuit, and the third logic circuit are each an OR circuit.

11. The light detecting device of claim 9 , wherein the first pixel further includes a first AND circuit, and wherein a first input node of the first AND circuit is coupled to an output node of the first inverter.

12. The light detecting device of claim 11 , wherein the plurality of pixels further includes a fourth pixel that includes a fourth avalanche diode, a fourth inverter, and a second AND circuit, wherein a first input node of the second AND circuit is coupled to the output node of the first inverter, wherein the first pixel and the fourth pixel are in a first column, and wherein a second input node of the first AND circuit and a second input node of the second AND circuit are coupled to a first select line.

13. The light detecting device of claim 11 , wherein the first input node of the first logic circuit is configured to receive an eighth output based on a seventh output of the first AND circuit.

14. The light detecting device of claim 9 , wherein an output node of the third logic circuit is coupled to a time measurement section.

15. The light detecting device of claim 9 , wherein the first avalanche diode, the second avalanche diode, and the third avalanche diode are in a first substrate, and wherein the first inverter, the second inverter, and the third inverter are in a second substrate stacked on the first substrate.

16. The light detecting device of claim 15 , wherein a time measurement section is disposed in the second substrate.

17. The light detecting device of claim 9 , wherein a second input node of the first logic circuit is coupled to a controller.

18. The light detecting device of claim 9 , wherein the first pixel, the second pixel, and the third pixel are adjacent to each other.

Priority Claims (1)

Continuity (2)

References Cited (61)