IP Library › Granted Patent US 12,332,804
Granted Patent B2
US 12,332,804 · App. 18/629,470 · Granted Jun 17, 2025

Zone-aware memory management in memory sub-systems

Inventor: Amit Bhardwaj (Hyderabad, IN)
Assignee: Micron Technology, Inc.
G06F12/10G06F12/0253G06F2212/1044G06F2212/657
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Quick Facts
Patent No.
US 12,332,804
App. No.
18/629,470
Granted
Jun 17, 2025
Kind
B2
Abstract

Disclosed is a system including a memory device having a plurality of physical memory blocks and associated with a logical address space that comprises a plurality of zones, wherein each zone comprises a plurality of logical block addresses (LBAs), and a processing device, operatively coupled with the memory device, to perform operations of receiving a request to store data referenced by an LBA associated with a first zone of the plurality of zones, obtaining a version identifier of the first zone, obtaining erase values for a plurality of available physical memory blocks of the memory device, selecting, in view of the version identifier of the first zone and the erase values, a first physical memory block of the plurality of available physical memory blocks, mapping a next available LBA within the first zone to the first physical memory block, and storing the data in the first physical memory block.

Claims (51)

1. A system comprising:

a memory device; and

a processing device, operatively coupled with the memory device, to perform operations comprising:

responsive to receiving a request to store data referenced in association with a first zone of a logical address space of the memory device, storing the data in a memory block (MB), wherein the MB is selected in view of a version identifier of the first zone, the version identifier characterizing a number of times the first zone has been invalidated, and wherein invalidating the first zone comprises invalidating multiple logical block addresses (LBAs) of the first zone.

2. The system of claim 1 , wherein the request is associated with an LBA of the first zone, the operations further comprising:

mapping the LBA to the MB.

3. The system of claim 1 , wherein invalidating multiple LBAs of the first zone comprises moving a write pointer to a starting LBA of the first zone.

4. The system of claim 1 , wherein the MB is selected in further view of a number of times the MB has been erased.

5. The system of claim 1 , the operations further comprising:

responsive to receiving a second request to store second data referenced in association with a second zone of the logical address space of the memory device, storing the second data in a second MB, wherein the second MB is selected in view of a second version identifier of the second zone, the second version identifier characterizing a number of times the second zone has been invalidated, wherein the second version identifier of the second zone is lower than the version identifier of the first zone, and wherein a number of times the second MB has been erased is higher than a number of times the second MB has been erased.

6. The system of claim 1 , wherein selecting the MB comprises:

determining that the version identifier of the first zone corresponds to a j-th lowest version identifier interval associated with a distribution of zones of the logical address space of the memory device, wherein j is a natural number that ranks, from lowest to highest, version identifier intervals by a number of times one or more zones of a respective version identifier interval have been invalidated; and

selecting the MB from a j-th highest erase count interval of a distribution of erase counts of at least a subset of a plurality of MBs of the memory device, wherein the plurality of MBs comprises the MB, wherein an erase count of an individual MB of the plurality of MBs characterizes a number of times the individual MB has been erased, and wherein i is further the natural number that ranks, from highest to lowest, erase count intervals by a number of times one or more MBs of a respective erase count interval have been erased.

7. The system of claim 1 , wherein the operations further comprise:

initiating a scan of the memory device;

scanning a plurality of MBs associated with the LBAs of the first zone;

identifying one or more MBs of the plurality of MBs as MBs that are at-risk of losing stored data;

copying the stored data from the one or more identified MBs that are at-risk of losing stored data to one or more additional MBs; and

responsive to a number of the one or more identified MBs that are at-risk of losing stored data satisfying a predetermined condition, stopping the scan of the memory device at the first zone.

8. A method comprising:

receiving, by a processing device operatively coupled with a memory device, a request to store data referenced in association with a first zone of a logical address space of the memory device; and

storing the data in a memory block (MB), wherein the MB is selected in view of a version identifier of the first zone, the version identifier characterizing a number of times the first zone has been invalidated, and wherein invalidating the first zone comprises invalidating multiple logical block addresses (LBAs) of the first zone.

9. The method of claim 8 , wherein the request is associated with an LBA of the first zone, the method further comprising:

mapping the LBA to the MB.

10. The method of claim 8 , wherein invalidating multiple LBAs of the first zone comprises moving a write pointer to a starting LBA of the first zone.

11. The method of claim 8 , wherein the MB is selected in further view of a number of times the MB has been erased.

12. The method of claim 8 , further comprising:

receiving a second request to store second data referenced in association with a second zone of the logical address space of the memory device; and

storing the second data in a second MB, wherein the second MB is selected in view of a second version identifier of the second zone, the second version identifier characterizing a number of times the second zone has been invalidated, wherein the second version identifier of the second zone is lower than the version identifier of the first zone, and wherein a number of times the second MB has been erased is higher than a number of times the second MB has been erased.

13. The method of claim 8 , wherein the MB is selected using operations comprising:

determining that the version identifier of the first zone corresponds to a j-th lowest version identifier interval associated with a distribution of zones of the logical address space of the memory device, wherein j is a natural number that ranks, from lowest to highest, version identifier intervals by a number of times one or more zones of a respective version identifier interval have been invalidated; and

selecting the MB from a j-th highest erase count interval of a distribution of erase counts of at least a subset of a plurality of MBs of the memory device, wherein the plurality of MBs comprises the MB, wherein an erase count of an individual MB of the plurality of MBs characterizes a number of times the individual MB has been erased, and wherein i is further the natural number that ranks, from highest to lowest, erase count intervals by a number of times one or more MBs of a respective erase count interval have been erased.

14. The method of claim 8 , further comprising:

initiating a scan of the memory device;

scanning a plurality of MBs associated with the LBAs of the first zone;

identifying one or more MBs of the plurality of MBs as MBs that are at-risk of losing stored data;

copying the stored data from the one or more identified MBs that are at-risk of losing stored data to one or more additional MBs; and

responsive to a number of the one or more identified MBs that are at-risk of losing stored data satisfying a predetermined condition, stopping the scan of the memory device at the first zone.

15. A non-transitory computer-readable memory storing instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

receiving a request to store data referenced in association with a first zone of a logical address space of a memory device; and

storing the data in a memory block (MB), wherein the MB is selected in view of a version identifier of the first zone, the version identifier characterizing a number of times the first zone has been invalidated, and wherein invalidating the first zone comprises invalidating multiple logical block addresses (LBAs) of the first zone.

16. The non-transitory computer-readable memory of claim 15 , wherein the request is associated with an LBA of the first zone, the operations further comprising:

mapping the LBA to the MB.

17. The non-transitory computer-readable memory of claim 15 , wherein the MB is selected in further view of a number of times the MB has been erased.

18. The non-transitory computer-readable memory of claim 17 , wherein the number of times the MB has been erased does not exceed a threshold value.

19. The non-transitory computer-readable memory of claim 15 , the operations further comprising:

receiving a second request to store second data referenced in association with a second zone of the logical address space of the memory device; and

storing the second data in a second MB, wherein the second MB is selected in view of a second version identifier of the second zone, the second version identifier characterizing a number of times the second zone has been invalidated, wherein the second version identifier of the second zone is lower than the version identifier of the first zone, and wherein a number of times the second MB has been erased is higher than a number of times the second MB has been erased.

20. The non-transitory computer-readable memory of claim 15 , wherein the MB is selected by:

determining that the version identifier of the first zone corresponds to a j-th lowest version identifier interval associated with a distribution of zones of the logical address space of the memory device, wherein j is a natural number that ranks, from lowest to highest, version identifier intervals by a number of times one or more zones of a respective version identifier interval have been invalidated; and

selecting the MB from a j-th highest erase count interval of a distribution of erase counts of at least a subset of a plurality of MBs of the memory device, wherein the plurality of MBs comprises the MB, wherein an erase count of an individual MB of the plurality of MBs characterizes a number of times the individual MB has been erased, and wherein j is further the natural number that ranks, from highest to lowest, erase count intervals by a number of times one or more MBs of a respective erase count interval have been erased.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2024
From: BHARDWAJ, AMIT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 067048/0035 →
Continuity (3)
Continuation 18094744 · Jan 9, 2023
Continuation 16946377 · Jun 18, 2020
Related Publication 20240256463A1 · Aug 1, 2024
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