Memory device and operating method of the memory device
There are provided a memory device and an operating method of the memory device. The memory device includes: a memory block including first select transistors, memory cells, and second select transistors, which are connected between bit lines and a source line; a precharge controller for monitoring a program operation of the memory cells, and changing a precharge mode of unselected strings among strings included in the memory block according to a monitoring result; and a select line voltage generator for generating a positive voltage or a negative voltage, which is applied to a second select line connected to the second select transistors, according to the precharge mode selected in the precharge controller.
1. A memory device comprising:
a memory block including first select transistors, memory cells, and second select transistors, which are connected between bit lines and a source line;
a precharge controller configured to monitor a program operation of the memory cells, and change a precharge mode of unselected strings among strings included in the memory block according to a monitoring result; and
a select line voltage generator configured to generate one of a positive voltage and a negative voltage, which is applied to a second select line connected to the second select transistors, according to the precharge mode selected in the precharge controller.
2. The memory device of claim 1 , wherein the precharge controller is configured to:
monitor target voltages of the memory cells in the program operation;
compare a selected target voltage among the target voltages with a reference voltage; and
change the precharge mode according to a comparison result.
3. The memory device of claim 2 , wherein the reference voltage is set as a voltage higher than an intermediate voltage among the target voltages.
4. The memory device of claim 2 , wherein, when the selected target voltage is equal to or lower than the reference voltage, the precharge controller controls the select line voltage generator such that the positive voltage is applied to the second select line.
5. The memory device of claim 2 , wherein, when the selected target voltage is higher than the reference voltage, the precharge controller controls the select line voltage generator such that the negative voltage is applied to the second select line.
6. The memory device of claim 1 , wherein the select line voltage generator is configured to generate the positive voltage to be applied to a first select line connected to the first select transistors as controlled by the precharge controller.
7. The memory device of claim 1 , further comprising:
a word line voltage generator configured to generate voltages to be applied to word lines connected to the memory cells; and
a source line voltage generator configured to generate a voltage to be applied to the source line.
8. The memory device of claim 7 , wherein the word line voltage generator is configured to:
generate one of a program voltage and a verify voltage, which is to be applied to a selected word line among the word lines; and
generate a pass voltage to be applied to unselected word lines among the word lines.
9. The memory device of claim 7 , wherein the word line voltage generator is configured to generate a pass voltage to be applied to the word lines, when the unselected strings are precharged.
10. The memory device of claim 7 , wherein the source line voltage generator is configured to generate a precharge voltage to be applied to the source line, when the unselected strings are precharged.
11. A memory device comprising:
a memory block including selected strings and unselected strings, which are connected between bit lines and a source line;
a source line voltage generator configured to apply a precharge voltage to the source line; and
a select line voltage generator configured to apply one of a positive voltage and a negative voltage to a first select line adjacent to the bit lines and a second select line adjacent to the source line, wherein the first select line and the second select line are connected to the selected strings and the unselected strings,
wherein the select line voltage generator is configured to:
apply the positive voltage to the second select line to precharge the unselected strings when a target voltage of memory cells of selected memory cells included in the selected strings is equal to or lower than a reference voltage; and
apply the negative voltage to the second select line to precharge the unselected strings when the target voltage is higher than the reference voltage.
12. The memory device of claim 11 , further comprising a precharge controller configured to compare the target voltage with the reference voltage, and control the select line voltage generator according to a comparison result.
13. The memory device of claim 11 , further comprising page buffers configured to apply a program allow voltage to bit lines connected to the selected strings among the bit lines, and apply a program inhibit voltage to bit lines connected to the unselected strings among the bit lines.
14. A method of operating a memory device, the method comprising:
comparing, with a reference voltage, a target voltage of selected memory cells among memory cells included in selected strings and unselected strings;
transmitting a precharge voltage supplied to a source line to the unselected strings by turning on select transistors included in the unselected strings when the target voltage is equal to or lower than the reference voltage, and transmitting the precharge voltage supplied to the source line to the unselected strings by using a leakage current of the select transistors when the target voltage is higher than the reference voltage; and
programming the selected memory cells.
15. The method of claim 14 , wherein the reference voltage is set as a voltage higher than an intermediate voltage among a plurality of target voltages of the selected memory cells.
16. The method of claim 14 , wherein a positive voltage is applied a select line connected to the select transistors such that the select transistors are turned on.
17. The method of claim 14 , wherein a negative voltage is applied to a select line connected to the select transistors such that the leakage current of the select transistors is used.
18. The method of claim 14 , wherein the programming of the selected memory cells includes:
applying a program voltage to a selected word line connected to the selected memory cells; and
applying a pass voltage to unselected word lines connected to unselected memory cells except the selected memory cells.
19. The method of claim 14 , further comprising verifying a threshold voltage of the selected memory cells after the programming of the selected memory cells.