Memory device and method of operating the same

1. A method of operating a memory device including a memory block including first and second sub blocks, the first sub block being connected to a first drain select line and a first source select line, the second sub block being connected to a second drain select line and a second source select line, and each of the first and second sub blocks being connected to a plurality of bit lines, a plurality of word lines, and a common source line, the method comprising:

discharging a verify voltage applied to a selected word line among the plurality of word lines; and

precharging a channel region of the memory block through the common source line,

wherein the precharging comprises applying a control voltage to the first source select line and the second source select line at different time points.

2. The method of claim 1 , wherein the precharging further comprises:

applying a word line voltage to one or more word lines of the plurality of word lines; and

applying a precharge voltage to the common source line while the word line voltage is applied to the one or more word lines.

3. The method of claim 2 , wherein the applying the word line voltage comprises:

applying the word line voltage to the selected word line and a first unselected word line group; and

applying a ground voltage to a second unselected word line group, while the word line voltage is applied to the selected word line and the first unselected word line group,

wherein the first unselected word line group includes unselected word lines positioned between the selected word line and the first or second drain select lines among the plurality of word lines, and

wherein the second unselected word line group includes unselected word lines positioned between the selected word line and the first or second source select lines among the plurality of word lines.

4. The method of claim 2 , wherein the applying the word line voltage comprises:

applying the word line voltage to the selected word line and a first unselected word line group; and

applying a ground voltage to a second unselected word line group while the word line voltage is applied to the selected word line and the first unselected word line group,

wherein the first unselected word line group includes unselected word lines on which a program operation is performed among the plurality of word lines, and

wherein the second unselected word line group includes unselected word lines on which the program operation is to be performed among the plurality of word lines.

5. The method of claim 1 ,

wherein the memory block further includes third and fourth sub blocks, and

wherein the precharging comprises:

applying the control voltage to the first source select line and a third source select line corresponding to the third sub block at a first time point; and

applying the control voltage to the second source select line and a fourth source select line corresponding to the fourth sub block at a second time point.

6. The method of claim 1 , wherein the control voltage is a voltage for turning on source select transistors connected to either of the first and second source select lines to transfer a precharge voltage applied through the common source line to a channel region of the memory block.

7. The method of claim 1 ,

wherein the first sub block comprises:

first drain select transistors connected to the plurality of bit lines, and controlled by the first drain select line;

first cell strings connected to the first drain select transistors, and controlled by the plurality of word lines; and

first source select transistors connected between the first cell strings and the common source line, and controlled by the first source select line,

wherein the second sub block comprises:

second drain select transistors connected to the plurality of bit lines, and controlled by the second drain select line;

second cell strings connected to the second drain select transistors, and controlled by the plurality of word lines; and

second source select transistors connected between the second cell strings and the common source line, and controlled by the second source select line.

8. A method of operating a memory device including a memory block including first and second sub blocks, the first sub block being connected to a first drain select line and a first source select line, the second sub block being connected to a second drain select line and a second source select line, and each of the first and second sub blocks being connected to a plurality of bit lines, a plurality of word lines, and a common source line, the method comprising:

discharging a verify voltage applied to a selected word line among the plurality of word lines; and

precharging a channel region of the memory block through the plurality of bit lines,

wherein the precharging comprises applying a control voltage to the first drain select line and the second drain select line at different time points.

9. The method of claim 8 , wherein the precharging further comprises:

applying a word line voltage to one or more word lines of the plurality of word lines; and

applying a precharge voltage to the plurality of bit lines while the word line voltage is applied to the one or more word lines.

10. The method of claim 9 , wherein the applying the word line voltage comprises:

applying the word line voltage to the selected word line and a first unselected word line group; and

applying a ground voltage to a second unselected word line group, while the word line voltage is applied to the selected word line and the first unselected word line group,

wherein the first unselected word line group includes unselected word lines positioned between the selected word line and the first or second source select lines among the plurality of word lines, and

wherein the second unselected word line group includes unselected word lines positioned between the selected word line and the first or second drain select lines among the plurality of word lines.

11. The method of claim 9 , wherein the applying the word line voltage comprises:

applying the word line voltage to the selected word line and a first unselected word line group; and

applying a ground voltage to a second unselected word line group while the word line voltage is applied to the selected word line and the first unselected word line group,

wherein the first unselected word line group includes unselected word lines on which a program operation is performed among the plurality of word lines, and

wherein the second unselected word line group includes unselected word lines on which the program operation is to be performed among the plurality of word lines.

12. The method of claim 8 ,

wherein the memory block further includes third and fourth sub blocks, and

wherein the precharging comprises:

applying the control voltage to the first drain select line and a third drain select line corresponding to the third sub block at a first time point; and

applying the control voltage to the second drain select line and a fourth drain select line corresponding to the fourth sub block at a second time point.

13. The method of claim 8 , wherein the control voltage is a voltage for turning on drain select transistors connected to either of the first and second source select lines to transfer a precharge voltage applied through the bit lines to a channel region of the memory block.

14. The method of claim 8 ,

wherein the first sub block comprises:

first drain select transistors connected to the plurality of bit lines and controlled by the first drain select line;

first cell strings connected to the first drain select transistors and controlled by the plurality of word lines; and

first source select transistors connected between the first cell strings and the common source line, and controlled by the first source select line,

wherein the second sub block comprises:

second drain select transistors connected to the plurality of bit lines, and controlled by the second drain select line;

second cell strings connected to the second drain select transistors, and controlled by the plurality of word lines; and

second source select transistors connected between the second cell strings and the common source line, and controlled by the second source select line.

15. A memory device comprising:

a memory block including a first sub block connected to a first drain select line and a first source select line, and a second sub block connected to a second drain select line and a second source select line, and each of the first and second sub blocks being connected to a plurality of bit lines, a plurality of word lines and a common source line;

a peripheral circuit configured to perform a program loop including a program voltage apply step of applying a program voltage to a selected word line among the plurality of word lines, a verify step of verifying a program state of memory cells connected to the selected word line, and a step of precharging a channel region of the memory block through the common source line; and a program operation controller configured to control the peripheral circuit to transfer a precharge voltage to the channel region through the common source line or the plurality of bit lines, in the step of precharging the channel region, wherein the program operation controller controls the peripheral circuit to apply a control voltage to the first and second source select lines at different time points or to apply the control voltage to the first and second drain select lines at different time points during the step of the pre-charging.

16. The memory device of claim 15 ,

wherein the first sub block comprises:

first drain select transistors connected to the plurality of bit lines, and controlled by the first drain select line;

first cell strings connected to the first drain select transistors, and controlled by the plurality of word lines; and

first source select transistors connected between the first cell strings and the common source line, and controlled by the first source select line,

wherein the second sub block comprises:

second drain select transistors connected to the plurality of bit lines, and controlled by the second drain select line;

second cell strings connected to the second drain select transistors, and controlled by the plurality of word lines; and

second source select transistors connected between the second cell strings and the common source line, and controlled by the second source select line.

17. The memory device of claim 16 , wherein the control voltage is a voltage for turning on the first and second drain select transistors or the first and second source select transistors to transfer the precharge voltage to the channel region.

18. The memory device of claim 15 ,

wherein the memory block further includes a third sub block connected to a third drain select line and a third source select line and a fourth sub block connected to a fourth drain select line and a fourth source select line, and

wherein the program operation controller controls, in the step of precharging the channel region, the peripheral circuit to

apply the control voltage to the first and third drain select lines at a first time point and

apply the control voltage to the second and fourth drain select lines at a second time point, or

apply the control voltage to the first and third source select lines at a third time point and

apply the control voltage to the second and fourth source select lines at a fourth time point.

19. An operating method of a memory device, the operating method comprising: applying a pre charge voltage to a common line or a plurality of bit lines; pre charging a channel region of cell strings through the common line or the plurality of bit lines according to whether the pre charge voltage is applied to either the common line or the plurality of bit lines; turning on a first source selection transistor and a second source selection transistor among selection transistors included in the cell strings at different time points by using a control voltage while the channel region is pre charged through the common line; and turning on a first drain selection transistor and a second drain selection transistor among the selection transistors at different time points by using the control voltage while the channel region is pre charged through the plurality of the bit lines, and wherein the cell strings are included in different memory regions.