Method of programming memory
A method of programming a memory includes performing a plurality of programming shots is provided. Each programming shot includes a pre-charge stage and a programming stage and includes the following steps. Applying a common source line voltage to a common source line or applying a bit line voltage to a bit line in the pre-charge stage, wherein the common source line voltage or the bit line voltage is applied by using incremental-step-pulse programming (ISSP) in the plurality of pre-charge stages. Applying a programming voltage to a selected word line in the programming stage, wherein the programming voltage is applied by using ISSP in the plurality of programming stages.
1. A method of programming a memory, comprising performing a plurality of programming shots, and each of the plurality of programming shots comprises a pre-charge stage and a programming stage and comprises following steps:
applying a common source line voltage to a common source line in the pre-charge stage, wherein the common source line voltage is applied by using incremental-step-pulse programming in a plurality of the pre-charge stages; and
applying a programming voltage to a selected word line in the programming stage, wherein the programming voltage is applied by using incremental-step-pulse programming in a plurality of the programming stages.
2. The method of programming the memory according to claim 1 , wherein the common source line voltage in the pre-charge stage is increased between one programming shot and a subsequent programming shot, and each values of the common source line voltage increased between the one programming shot and the subsequent programming shot are the same.
3. The method of programming the memory according to claim 1 , wherein the plurality of programming shots comprises a first period and a second period, the common source line voltage in the pre-charge stage is unchanged between one programming shot and a subsequent programming shot of the first period, and the common source line voltage in the pre-charge stage is increased between one programming shot and a subsequent programming shot of the second period.
4. The method of programming the memory according to claim 3 , wherein the plurality of programming shots comprise one first period and one second period arranged in sequence, and each values of the common source line voltage between the one programming shot and the subsequent programming shot in the second period are the same.
5. The method of programming the memory according to claim 3 , wherein the plurality of programming shots comprise a plurality of first periods and a plurality of second periods, and one of the plurality of second periods is arranged between neighbor two of the plurality of first periods.
6. The method of programming the memory according to claim 3 , wherein the plurality of programming shots comprise two first periods and one second period, and the one second period is arranged between the two first periods.
7. The method of programming the memory according to claim 1 , further comprising applying a pre-charge voltage to a ground select line and a plurality of bottom dummy word lines in the pre-charge stage.
8. The method of programming the memory according to claim 1 , further comprising applying a ground voltage to a string select line in the pre-charge stage to make a string select gate coupled to the string select line in an off state.
9. The method of programming the memory according to claim 1 , further comprising performing a quick pass write in the plurality of programming shots.
10. The method of programming the memory according to claim 1 , wherein the memory comprises a memory cell including a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC).
11. A method of programming a memory, comprising performing a plurality of programming shots, and each of the plurality of programming shots comprises a pre-charge stage and a programming stage and comprises following steps:
applying a bit line voltage to a bit line in the pre-charge stage, wherein the bit line voltage is applied by using incremental-step-pulse programming in a plurality of the pre-charge stages; and
applying a programming voltage to a selected word line in the programming stage, wherein the programming voltage is applied by using incremental-step-pulse programming in a plurality of the programming stages.
12. The method of programming the memory according to claim 11 , wherein the bit line voltage in the pre-charge stage is increased between one programming shot and a subsequent programming shot, and each values of the bit line voltage between the one programming shot and the subsequent programming shot are the same.
13. The method of programming the memory according to claim 11 , wherein the plurality of programming shots comprise a first period and a second period, the bit line voltage in the pre-charge stage is unchanged between one programming shot and a subsequent programming shot of the first period, and the bit line voltage in the pre-charge stage is increased between one programming shot and a subsequent programming shot of the second period.
14. The method of programming the memory according to claim 13 , wherein the plurality of programming shots comprise one first period and one second period arranged in sequence, and difference values of the common source line voltage between the one programming shot and the subsequent programming shot in the second period are the same.
15. The method of programming the memory according to claim 13 , wherein the plurality of programming shots comprise a plurality of first periods and a plurality of second periods, and one of the plurality of second periods is arranged between neighbor two of the plurality of first periods.
16. The method of programming the memory according to claim 13 , wherein the plurality of programming shots comprise two first periods and one second period, and the one second period is arranged between the two first periods.
17. The method of programming the memory according to claim 11 , further comprising applying a pre-charge voltage to a string select line and a plurality of top dummy word lines in the pre-charge stage.
18. The method of programming the memory according to claim 11 , further comprising applying a ground voltage to a ground select line in the pre-charge stage to make a ground select gate coupled to the ground select line in an off state.
19. The method of programming the memory according to claim 11 , further comprising performing a quick pass write in the plurality of programming shots.
20. The method of programming the memory according to claim 11 , wherein the memory comprises a memory cell including a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC).