Granted Patent B2

US 12,334,144 · App. 17/890,693 · Granted Jun 17, 2025

Inventor: Hyunsung Hong (Kanata, CA)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

G11C11/418

Abstract

Claims (50)

1. A memory device comprising:

a set of memory cells coupled to a word line;

a tracking cell coupled to a tracking word line and a tracking bit line;

a tracking booster circuit coupled to the tracking word line, the tracking booster circuit configured to boost a first edge of a first pulse applied to the tracking word line thereby causing the first edge to become sharper, the tracking cell configured to generate a second pulse at the tracking bit line, in response to the first pulse having the boosted first edge; and

a word line controller configured to apply a third pulse to the word line, based on the second pulse.

2. The memory device of claim 1 , further comprising:

a booster circuit coupled to the set of memory cells, the booster circuit to boost a second edge of the third pulse applied to the word line.

3. The memory device of claim 1 , wherein the tracking booster circuit is to selectively boost the first edge of the first pulse, in response to a control signal having a first state.

4. The memory device of claim 1 , wherein the tracking cell is to generate a second edge of the second pulse at the tracking bit line, in response to the boosted first edge of the first pulse.

5. The memory device of claim 4 , wherein the word line controller is to apply a third edge of the third pulse to the word line, based on the second edge of the second pulse.

6. The memory device of claim 5 ,

wherein the first edge is a rising edge of the first pulse,

wherein the second edge is a falling edge of the second pulse, and

wherein the third edge is a falling edge of the third pulse.

7. The memory device of claim 1 , wherein the tracking booster circuit includes:

a NAND gate including a first input port coupled to the tracking word line; and

a transistor including:

a gate electrode coupled to an output port of the NAND gate, and

a drain electrode coupled to the tracking word line.

8. The memory device of claim 7 , wherein the NAND gate includes a second input port to receive a control signal to enable or disable the tracking booster circuit.

9. The memory device of claim 7 , wherein the transistor is a P-type transistor.

10. A memory device comprising:

a memory array including:

a first set of memory cells coupled to a bit line, at least one of the first set of memory cells coupled to a first word line, and

a second set of memory cells coupled to a second word line, wherein the second set of memory cells has a larger number of memory cells than the first set of memory cells;

a first booster circuit coupled to the first word line, the first booster circuit configured to boost a first edge of a first pulse applied to the first word line thereby causing the first edge of the first pulse to become sharper, the at least one of the first set of memory cells configured to generate a second pulse at the bit line, in response to the first pulse having the boosted first edge;

a word line controller configured to apply a third pulse to the second word line, based on the second pulse; and

a second booster circuit coupled to the second word line, the second booster circuit configured to boost a second edge of the third pulse applied to the second word line thereby causing the second edge of the third pulse to become sharper.

11. The memory device of claim 10 , wherein the at least one of the first set of memory cells is to generate a third edge of the second pulse at the bit line, in response to the boosted first edge of the first pulse.

12. The memory device of claim 11 , wherein the word line controller is to apply a fourth edge of the third pulse subsequent to the second edge, based on the third edge of the second pulse.

13. The memory device of claim 12 ,

wherein the first edge is a rising edge of the first pulse,

wherein the second edge is a rising edge of the third pulse,

wherein the third edge is a falling edge of the second pulse, and

wherein the fourth edge is a falling edge of the third pulse.

14. A method comprising:

generating, by a memory controller, a first pulse having a first edge;

boosting, by the memory controller, the first edge of the first pulse thereby causing the first edge of the first pulse to become sharper;

applying, by the memory controller, the first pulse having the boosted first edge to a tracking word line coupled to a tracking cell, the tracking cell to generate a second pulse at a tracking bit line coupled to the tracking cell, responsive to the first pulse having the boosted first edge;

generating, by the memory controller, a third pulse;

boosting, by the memory controller, a second edge of the third pulse thereby causing the second edge of the third pulse to become sharper; and

applying, by the memory controller, the third pulse having the boosted second edge to a word line coupled to a set of memory cells, the third pulse having a pulse width based on the second pulse at the tracking bit line.

15. The method of claim 14 ,

wherein the tracking cell is to generate a third edge of the second pulse at the tracking bit line, in response to the boosted first edge of the first pulse, and

wherein generating, by the memory controller, the third pulse based on the second pulse at the tracking bit line includes generating, by the memory controller, a fourth edge of the third pulse subsequent to the second edge of the third pulse, based on the third edge of the second pulse.

16. The memory device of claim 14 , further comprising a tracking booster circuit.

17. The memory device of claim 16 , wherein the tracking booster circuit comprises a NAND gate including a first input port coupled to a tracking word line.

18. The memory device of claim 17 , wherein the tracking booster circuit further comprises a transistor coupled to the NAND gate.

19. The memory device of claim 18 , wherein the transistor comprises a gate electrode coupled to an output port of the NAND gate.

20. The memory device of claim 19 , wherein the transistor further comprises a drain electrode coupled to the tracking word line.

Assignments (1)

Continuity (2)

References Cited (18)