Time-interleaved analog to digital converter based on flash analog to digital conversion
A time-interleaved analog to digital converter (ADC) includes capacitor array circuits, a flash ADC, first and second circuits, a converter, and an encoder circuit. The capacitor array circuits sample an input signal and generate first residue signals according to first quantization signals. The flash ADC samples the input signal and generates the first quantization signals. The first circuits transfer the first residue signals from the capacitor array circuits. The converter performs a signal conversion according to the first and the second residue signals to generate a second quantization signal. The second circuits transfer second residue signals to the converter. The capacitor array circuits further generate the second residue signal in response to the signal conversion. The encoder circuit generates a digital output according to one of the first quantization signals and the second quantization signals.
1. A time-interleaved analog to digital converter, comprising:
a plurality of capacitor array circuits configured to sequentially sample an input signal and generate a plurality of first residue signals according to a plurality of first quantization signals;
a flash analog to digital converter circuitry configured to sample the input signal and sequentially generate the plurality of first quantization signals;
a plurality of first transfer circuits configured to sequentially transfer the plurality of first residue signals from the plurality of capacitor array circuits according to a plurality of first control signals;
a converter circuitry configured to perform a noise shaping signal conversion according to a first signal in the plurality of first residue signals and a second signal in plurality of second residue signals, in order to generate a second quantization signal;
a plurality of second transfer circuits configured to sequentially transfer a plurality of second residue signals from the plurality of capacitor array circuits to the converter circuitry according to a plurality of second control signals, wherein the plurality of capacitor array circuits further generate the plurality of second residue signals in response to the noise shaping signal conversion; and
an encoder circuit configured to generate a digital output according to a second quantization signal and a corresponding signal of the plurality of first quantization signals.
2. The time-interleaved analog to digital converter of claim 1 , wherein the flash analog to digital converter circuitry and one of the plurality of capacitor array circuits sample the input signal concurrently.
3. The time-interleaved analog to digital converter of claim 1 , wherein the flash analog to digital converter circuitry comprises a plurality of flash analog to digital converter circuits, and the plurality of flash analog to digital converter circuits are configured to sequentially sample the input signal and generate the plurality of first quantization signals according to the sampled input signal.
4. The time-interleaved analog to digital converter of claim 3 , further comprising:
a control logic circuit configured to generate a digital code according to the corresponding signal,
wherein one of the plurality of capacitor array circuits is further configured to generate one of the plurality of first residue signals according to the digital code, and the encoder circuit is further configured to generate the digital output according to the digital code and the second quantization signal.
5. The time-interleaved analog to digital converter of claim 3 , wherein a number of the plurality of flash analog to digital converter circuits is the same as a number of the plurality of capacitor array circuits.
6. The time-interleaved analog to digital converter of claim 3 , wherein one of the plurality of flash analog to digital converter circuits comprises:
a sampling circuit configured to sample the input signal to generate a sampled input signal;
a voltage generator circuit configured to generate a plurality of voltages;
a plurality of comparator circuits configured to compare the sampled input signal with each of the plurality of voltages to generate a plurality of decision signals; and
a codec circuit configured to generate a plurality of bits in one of the plurality of first quantization signals according to the plurality of decision signals.
7. The time-interleaved analog to digital converter of claim 1 , further comprising:
a control logic circuit configured to generate a digital code according to the corresponding signal and output the digital code to a corresponding one of the plurality of capacitor array circuits according to a plurality of enable signals,
wherein the corresponding one of the plurality of capacitor array circuits generates a corresponding one of the plurality of first residue signals according to the digital code, and the encoder circuit is further configured to generate the digital output according to the digital code and the second quantization signal.
8. The time-interleaved analog to digital converter of claim 1 , wherein the converter circuitry performs the noise shaping signal conversion according to the first signal and the second signal during a conversion phase, the first signal is from a first capacitor array circuit in the plurality of capacitor array circuits, a second capacitor array circuit in the plurality of capacitor array circuits samples the input signal during a sampling phase, and the conversion phase and the sampling phase are partially overlapped.
9. The time-interleaved analog to digital converter of claim 8 , wherein the conversion phase is longer than the sampling phase.
10. The time-interleaved analog to digital converter of claim 1 , wherein the converter circuitry performs the noise shaping signal conversion according to the first signal and the second signal during a first conversion phase, the flash analog to digital converter circuitry generate the plurality of first quantization signals during a second conversion phase, and the first conversion phase and the second conversion phase are partially overlapped.
11. The time-interleaved analog to digital converter of claim 10 , wherein the first conversion phase is longer than the second conversion phase.
12. The time-interleaved analog to digital converter of claim 1 , wherein the encoder circuit is configured to combine a digital code and the second quantization signal to be the digital output, the digital code is generated according to the corresponding signal, and one of the plurality of capacitor array circuits and the flash analog to digital converter sample the input signal concurrently to respectively generate the first signal and the second signal.
13. The time-interleaved analog to digital converter of claim 1 , wherein the converter circuitry comprises:
a noise shaping circuit configured to process the second signal to generate a third signal; and
a quantizer circuit configured to perform a quantization according to the third signal and the first signal to generate the second quantization signal.
14. The time-interleaved analog to digital converter of claim 1 , wherein the flash analog to digital converter circuitry comprises only one flash analog to digital converter circuit.