Data preprocessing (DPP) pattern supporting both normal program and early cache release program (ECRP)

1. A memory device comprising:

page buffers, each of the page buffers comprising N data latches configured to store data, where N is a positive integer; and

a controller coupled to the page buffers and configured to:

receive data that includes data units, wherein each of the data units includes N bits;

store the data units in the N data latches;

convert the data stored in the N data latches based on a table; and

program cells of the memory device based on the converted data,

wherein the table include N rows and 2 N columns of bits; and

wherein bits from column 2 N−1 +2 to column 2 N in N th row of the table are identical.

2. The memory device of claim 1 , wherein L th column of the table contains K number of “0” in N rows of the L th column, and N rows of M th column of the table contain less than or equal to K number of “0”;

wherein L, K, and M are positive integers; and

wherein L is less than M.

3. The memory device of claim 1 , wherein second column of the table contains N number of “0” in N rows of the second column, and N rows of X th column of the table contain less than N number of “0”, and wherein X is greater than 2, where X is a positive integer.

4. The memory device of claim 1 , wherein columns of the table correspond to a set of respective voltage levels.

5. The memory device of claim 1 , wherein to store the data units in the N data latches, the controller is further configured to:

store J th bit of each of the data units in J th data latch,

where J is a positive integer.

6. The memory device of claim 1 , wherein to program the cells of the memory device based on the converted data, the controller is further configured to:

determine the converted data match a target column of the table;

determine a target voltage level corresponding to the target column;

determine one or more cells of the cells of the memory device corresponding to the converted data; and

program the one or more cells to the target voltage level.

7. The memory device of claim 6 , wherein the controller is further configured to verify the one or more cells, the controller is configured to:

determine the target column of the table contains one or more “0” bits;

determine the one or more cells based on the converted data;

verify the voltage levels of the one or more cells;

in response to the voltage levels of the one or more cells are higher than a voltage requirement; and

convert the one or more “0” bits in the data latch corresponding to the one or more cells to “1” bits.

8. The memory device of claim 7 , wherein the controller is further configured to:

determine that the target column is column 2 N−1 +1 of the table; and

release N th data latch of the memory device.

9. The memory device of claim 7 , wherein the controller is further configured to:

in response to the target column is column 2 N −1 or 2 N of the table, determine the one or more cells based on the converted data and data stored in a DS data latch of the page buffer.

10. The memory device of claim 1 , wherein Nis greater than or equal to 3.

11. A memory system, comprising:

a memory device, comprising:

page buffers, each of the page buffers comprising N data latches configured to store data, where N is a positive integer; and

a controller coupled to the page buffers and configured to:

receive data that includes data units, wherein each of the data units includes N bits;

store the data units in the N data latches;

convert the data stored in the N data latches based on a table; and

program cells of the memory device based on the converted data,

wherein the table include N rows and 2 N columns of bits; and

wherein bits from column 2 N−1 +2 to column 2 N in N th row of the table are identical; and

a host controller coupled to the memory device and configured to control the memory device.

12. The memory system of claim 11 , wherein L th column of the table contains K number of “0” in N rows of the L th column, and N rows of M th column of the table contain less than or equal to K number of “0”;

wherein L, K, and M are positive integers; and

wherein L is less than M.

13. The memory system of claim 11 , wherein second column of the table contains N number of “0” in N rows of the second column, and N rows of X th column of the table contain less than N number of “0”, and wherein X is greater than 2.

14. The memory system of claim 11 , wherein columns of the table correspond to a set of respective voltage levels.

15. The memory system of claim 11 , wherein to store the data units in the N data latches, the controller is further configured to:

store J th bit of each of the data units in J th data latch,

where J is a positive integer.

16. The memory system of claim 11 , wherein to program the cells of the memory device based on the converted data, the controller is further configured to:

determine the converted data match a target column of the table;

determine a target voltage level corresponding to the target column;

determine one or more cells of the cells of the memory device corresponding to the converted data; and

program the one or more cells to the target voltage level.

17. The memory device of claim 16 , wherein the controller is further configured to verify the one or more cells, the controller is configured to:

determine the target column of the table contains one or more “0” bits;

determine the one or more cells based on the converted data;

verify the voltage levels of the one or more cells;

in response to the voltage levels of the one or more cells are higher than a voltage requirement; and

convert the one or more “0” bits in the data latch corresponding to the one or more cells to “1” bits.

18. The memory system of claim 17 , wherein the controller is further configured to:

determine that the target column is column 2 N−1 +1 of the table; and

release N th data latch of the memory device.

19. The memory system of claim 11 , wherein N is greater than or equal to 3.

20. A method for operating a memory device, comprising:

receiving data that includes data units, wherein each of the data units includes N bits, wherein N is a positive integer;

storing the data units in N data latches;

converting the data stored in the N data latches based on a table; and

programing cells of the memory device based on the converted data,

wherein the table include N rows and 2 N columns of bits; and

wherein bits from column 2 N−1 +2 to column 2 N in N th row of the table are identical.