Memory device and manufacturing method thereof

1. A memory device, comprising:

memory cells, each comprising:

a resistance variable storage device; and

an ovonic threshold switch (OTS) selector, stacked with the resistance variable storage device and coupled to the resistance variable storage device with a shared terminal, and comprising a switching layer formed of a chalcogenide compound comprising germanium, carbon, tellurium and nitrogen, wherein nitrogen atoms establish bonding with carbon atoms and germanium atoms in the chalcogenide compound.

2. The memory device according to claim 1 , wherein the chalcogenide compound is N W Ge X C Y Te Z , where a summation of “W”, “X”, “Y”, “Z” equals to 1.

3. The memory device according to claim 1 , wherein a total atomic ratio of nitrogen and germanium in the chalcogenide compound ranges from about 0.10 to about 0.30.

4. The memory device according to claim 1 , wherein a ratio of an atomic ratio of nitrogen in the chalcogenide compound over a total atomic ratio of nitrogen and germanium in the chalcogenide compound ranges from about 0.2 to about 0.55.

5. The memory device according to claim 1 , wherein an atomic ratio of nitrogen in the chalcogenide compound ranges from about 0.02 to about 0.165, an atomic ratio of germanium in the chalcogenide compound ranges from about 0.045 to about 0.24, an atomic ratio of carbon in the chalcogenide compound ranges from about 0.1 to about 0.3, and an atomic ratio of tellurium in the chalcogenide compound ranges from about 0.5 to about 0.7.

6. The memory device according to claim 1 , wherein a thickness of the switching layer ranges from about 3 nm to about 50 nm.

7. The memory device according to claim 1 , wherein a sidewall of a stacking structure of the OTS selector and the resistance variable storage device is laterally recessed at an electrode of the resistance variable storage device not shared with the OTS selector.

8. The memory device according to claim 1 , wherein a sidewall of a stacking structure of the OTS selector and the resistance variable storage device is laterally recessed at a lower portion of a storage layer of the resistance variable storage device.

9. The memory device according to claim 1 , wherein a sidewall of a stacking structure of the OTS selector and the resistance variable device is substantially flat from a top end to a bottom end of the stacking structure.

10. A manufacturing method of a memory device, comprising:

providing first signal lines over a semiconductor substrate;

providing stacking structures on the first signal lines, wherein the stacking structures respectively comprise a resistance variable storage device and an OTS selector stacked with the resistance variable storage device and coupled to the resistance variable storage device with a shared terminal, the OTS selector comprises a switching layer formed of a GeCTe compound doped with nitrogen, and nitrogen atoms establish bonding with carbon atoms and germanium atoms in the GeCTe compound doped with nitrogen; and

forming second signal lines on the stacking structures, wherein the second signal lines intersect with the first signal lines, and the stacking structures are located at intersections of the first and second signal lines.

11. The manufacturing method of the memory device according to claim 10 , wherein a method for forming the switching layer comprises a reactive sputtering process using a germanium target and a tellurium carbide target, and the germanium target is at least partially nitrided by nitrogen plasma during the reactive sputtering process.

12. The manufacturing method of the memory device according to claim 10 , wherein a method for forming the switching layer comprises a sputtering process using a germanium nitride target and a tellurium carbide target.

13. The manufacturing method of the memory device according to claim 12 , wherein a method for forming the switching layer comprises a sputtering process using a germanium target and a tellurium carbide target, and further comprises a nitridation process for further incorporating nitrogen into a deposited GeCTe compound.

14. The manufacturing method of the memory device according to claim 11 , wherein nitrogen gas and sputtering gas are introduced and ionized during the reactive sputtering process.

15. The manufacturing method of the memory device according to claim 11 , wherein nitrogen gas is not introduced during the reactive sputtering process.

16. The manufacturing method of the memory device according to claim 15 , wherein the method for forming the switching layer further comprises a nitridation process for introducing nitrogen into a GeCTe compound obtained from the reactive sputtering process.

17. A memory device, comprising:

first signal lines;

second signal lines, running over and intersecting the first signal lines; and

memory cells, each defined at an intersection of one of the first signal lines and one of the second signal lines, and respectively comprising:

a resistance variable storage device; and

an ovonic threshold switch (OTS) selector, stacked with the resistance variable storage device and coupled to the resistance variable storage device with a shared terminal, and comprising a switching layer formed of a GeCTe compound doped with nitrogen, wherein nitrogen atoms establish bonding with carbon atoms and germanium atoms in the GeCTe compound doped with nitrogen.

18. The memory device according to claim 17 , wherein the GeCTe compound doped with nitrogen is free of arsenic.

19. The memory device according to claim 17 , wherein the resistance variable storage device has a storage layer formed of a chalcogenide compound comprising germanium, tellurium and antimony.

20. The memory device according to claim 17 , wherein the resistance variable storage device includes a storage layer formed of a high-k dielectric material.