Transistor with gate attached field plate
An apparatus includes a substrate and a transistor disposed on the substrate. The transistor can include a gate disposed between a source area and a drain area of the transistor. The transistor can also include a plurality of routing lanes above the gate for use by automated routing programs that layout metal connections for the apparatus. A first field plate can be disposed above a LDD region of the source area with the first field plate being on a same level as the plurality of routing lanes. A second field plate can be disposed above a LDD region of the drain area with the second field plate being on the same level as the plurality of routing lanes. The first and second field plates can be electrically connected to the gate using respective first and second path that bypass the plurality of routing lanes.
1. An apparatus, comprising:
a substrate; and
a transistor disposed on the substrate, the transistor including,
a gate disposed between a source area and a drain area of the transistor,
a plurality of routing lanes above the gate for depositing metal connections,
a first field plate disposed above a lightly doped region (LDD region) of the source area, the first field plate being on a same level as the plurality of routing lanes,
a second field plate disposed above a LDD region of the drain area, the second field plate being on the same level as the plurality of routing lanes, and
wherein the first and second field plates are electrically connected to the gate using respective first and second paths that bypass the plurality of routing lanes.
2. The apparatus of claim 1 , further comprising:
a first tab connection that is disposed outside an active area of the transistor, the first path including the tab connection, and
a second tab connection that is disposed outside the active area of the transistor, the second path including the second tab connection.
3. The apparatus of claim 2 , wherein the first and second field plates are configured to extend over the respective first and second tab connections,
wherein the first and second field plates are further configured to overlap with the tab connection, and
wherein the first and second field plates are electrically connected to the respective first and second tab connections.
4. The apparatus of claim 3 , wherein the overlap is in a range of 100 nm to 300 nm.
5. The apparatus of claim 2 , wherein the first and second tab connections are formed over a thin oxide layer that is in a range of 10 Å to 80 Å.
6. The apparatus of claim 2 , wherein the first and second tab connection are formed over a thick oxide layer that is in a range of 200 Å to 500 Å.
7. The apparatus of claim 2 , wherein the first and second tab connections are offset from an edge of the active area by a distance in a range of 10 nm to 120 nm.
8. The apparatus of claim 2 , wherein the first and second field plates are electrically connected to the respective first and second tab connections using vias.
9. The apparatus of claim 2 , wherein the first and second field plates are electrically connected to the respective first and second tab connections using corresponding first and second metal connection plates, and
wherein the first and second metal connection plates extend over a full length of the respective overlapped portions of the first and second field plates in a length direction.
10. The apparatus of claim 2 , further comprising:
a first notch area in the first LDD region that is separate from the active area, the first notch area arranged adjacent the gate such that the first notch area is within an outermost edge of the active area in a width direction of the transistor, and
a second notch area in the second LDD region that is separate from the active area, the second notch area arranged adjacent the gate such that the second notch area is within the outermost edge of the active area in the width direction of the transistor.
11. The apparatus of claim 10 , wherein at least a portion of the first and second tab connections are formed within the respective first and second notch areas.
12. The apparatus of claim 1 , further comprising:
a gate layer extension that is disposed beyond the edge of an active area and connected to the gate,
wherein the first and second tab connections are connected to opposite sides of the gate layer extension.
13. A method, comprising:
depositing a gate layer beyond an edge of an active area a transistor to form a gate layer extension;
depositing at least one of a polysilicon layer or a WSix layer extending from the gate layer extension in a region outside the active area to form a first tab connection;
depositing at least one of a polysilicon layer or a WSix layer extending from the gate layer extension on an opposite side of the gate layer in the region outside the active area to form a second tab connection;
depositing a first field plate above a lightly doped region (LDD region) on a source side of the transistor, the first field plate extending over the first tab connection and overlapping the first tab connection as viewed from the top;
depositing a second field plate above a LDD region on a drain side of the transistor, the second field plate extending over the second tab connection and overlapping the second tab connection as viewed from the top;
connecting the first field plate to the first tab connection to electrically connect the first field plate to the gate; and
connecting the second field plate to the second tab connection to electrically connect the second field plate to the gate.
14. The method of claim 13 , wherein the first and second field plates overlap the respective first and second tab connections, and
wherein the overlap is in a range 100 nm to 300 nm.
15. The method of claim 13 , further comprising:
depositing an oxide layer prior to forming the first and second tab connections over the oxide layer,
wherein the oxide layer is in a range of 200 Å to 500 Å.
16. The method of claim 13 , wherein the first and second tab connections are offset from the edge of the active area by a distance in a range of 10 nm to 120 nm.
17. The method of claim 13 , further comprising:
forming a first notch area in the first LDD region that is separate from the active area, the first notch area arranged adjacent a gate of the transistor such that the first notch area is within an outermost edge of the active area in a width direction of the transistor; and
forming a second notch area in the second LDD region that is separate from the active area, the second notch area arranged adjacent the gate of the transistor such that the second notch area is within the outermost edge of the active area in the width direction of the transistor,
wherein at least a portion of the first and second tab connections are formed within the respective first and second notch areas.
18. An apparatus, comprising:
a substrate;
a transistor disposed on the substrate, the transistor including,
a gate disposed between a source area and a drain area of the transistor,
a first field plate disposed above a lightly doped region (LDD region) of the source area,
a second field plate disposed above a LDD region of the drain area,
a first tab connection that is disposed outside an active area of the transistor, the first field plate configured to extend over the first tab connection and overlap with the first tab connection, the first field plate electrically connected to the first tab connection, and
a second tab connection that is disposed outside the active area of the transistor, the second field plate is configured to extend over the second tab connection and overlap with the second tab connection, the second field plate electrically connected to the second tab connection; and
a gate layer extension that is disposed beyond an edge of the active area and connected to the gate,
wherein the first and second tab connections are connected to opposite sides of the gate layer extension.
19. An apparatus, comprising:
a substrate; and
a transistor disposed on the substrate, the transistor including,
a gate disposed between a source area and a drain area of the transistor,
a first field plate disposed above a lightly doped region (LDD region) of the source area,
a second field plate disposed above a LDD region of the drain area,
a first tab connection that is disposed outside an active area of the transistor, the first field plate configured to extend over the first tab connection and overlap with the first tab connection, the first field plate electrically connected to the first tab connection, and
a second tab connection that is disposed outside the active area of the transistor, the second field plate is configured to extend over the second tab connection and overlap with the second tab connection, the second field plate electrically connected to the second tab connection,
wherein the first and second LDD regions of the transistor have a first acceptable applied dose range for applying an implant dose in the first and second LDD regions,
wherein the apparatus further comprises:
a drain attached field plate (DAFP) transistor disposed on the substrate, the DAFP transistor having at least one third LDD region,
wherein the at least one third LDD region has a second acceptable applied dose range for applying the implant dose, and
wherein the first acceptable dose range at least partially overlaps with the second acceptable dose range.