Method for manufacturing semiconductor device with passing gate
The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a first trench in a substrate, disposing a first gate electrode in the first trench, and disposing a dummy gate electrode on the first gate electrode in the first trench. The method also includes removing the dummy gate electrode from the first gate electrode and forming a first doped region in the first gate electrode.
1. A method of manufacturing a semiconductor device, comprising:
forming a first trench in a substrate;
depositing a barrier layer in the first trench;
disposing a first gate electrode on the barrier layer to fill the first trench;
disposing a dummy gate electrode on the first gate electrode and the barrier layer in the first trench;
removing the dummy gate electrode from the first gate electrode and the barrier layer; and
implanting a dopant into a top surface of the first gate electrode to form a first doped region in the first gate electrode and implanting the dopant into an upper portion of the barrier layer, wherein the upper portion of the barrier layer surrounds the first doped region of the first gate electrode.
2. The method of claim 1 , further comprising: forming a second doped region in an active region of the substrate.
3. The method of claim 1 , further comprising:
forming a second trench in the substrate;
disposing a second gate electrode in the second trench; and
disposing a third gate electrode on the second gate electrode in the second trench.
4. The method of claim 3 , further comprising: providing a mask on the third gate electrode.
5. The method of claim 4 , wherein the mask defines the first doped region.
6. The method of claim 4 , further comprising: forming a third doped region in the third gate electrode.
7. The method of claim 6 , wherein the mask is removed from the third gate electrode before forming the third doped region.
8. The method of claim 1 , further comprising: disposing a capping layer on the first doped region.
9. A method of manufacturing a semiconductor device, comprising:
providing a substrate having a first trench; and
forming a first gate structure in the first trench, wherein the first gate structure includes a barrier layer in the first trench, and a first gate electrode on the barrier layer to fill the first trench, wherein the first gate electrode includes a first doped region;
wherein forming the first gate structure comprises:
disposing the first gate electrode in the first trench; and
implanting a dopant into a top surface of the first gate electrode to form the first doped region in an upper portion of the first gate electrode and implanting the dopant into an upper portion of the barrier layer, wherein the upper portion of the barrier layer surrounds the first doped region of the first gate electrode.
10. The method of claim 9 , wherein forming the first gate structure further comprises forming a first capping layer on the first gate electrode.
11. The method of claim 10 , wherein the first capping layer directly contacts the first gate electrode.
12. The method of claim 10 , wherein the first doped region is adjacent to the first capping layer.
13. The method of claim 9 , wherein the substrate comprises an isolation region and an active region, and the first trench is in the isolation region.
14. The method of claim 13 , wherein the active region has a second doped region adjacent to the isolation region, and wherein the first doped region of the first gate structure and the second doped region are of the same polarity type.
15. The method of claim 14 , wherein the second doped region comprises a source/drain (S/D) region.
16. The method of claim 9 , further comprising: forming a second gate structure in a second trench, wherein the second gate structure includes a second gate electrode and a third gate electrode on the second gate electrode.
17. The method of claim 16 , wherein the third gate electrode of the second gate structure has a third doped region.
18. The method of claim 17 , wherein the third doped region of the second gate structure and the first doped region of the first gate structure are of the same polarity type.
19. The method of claim 17 , wherein the third doped region of the second gate structure and the first doped region of the first gate structure have different dopant concentrations.
20. The method of claim 16 , wherein forming the first gate structure further comprises forming a first capping layer on the first gate electrode, and the second gate structure further comprises a second capping layer on the third gate electrode, wherein a bottom surface of the first capping layer and a bottom surface of the second capping layer are located at different elevations, wherein the first doped region is defined in the first gate electrode and the barrier layer.