Semiconductor structure and manufacturing method thereof

1. A semiconductor structure, comprising:

a substrate comprising a capacitor region;

a first isolation structure disposed in the substrate in the capacitor region; and

a capacitor, located in the capacitor region, and comprising:

the substrate in the capacitor region;

an electrode layer disposed in the substrate in the capacitor region; and

a first dielectric layer disposed between the electrode layer and the substrate and between the electrode layer and the first isolation structure, wherein the first dielectric layer is in direct contact with the first isolation structure,

wherein the substrate further comprises a memory cell region, and the semiconductor structure further comprises:

a second isolation structure disposed in the substrate in the memory cell region;

a gate electrode disposed in the substrate in the memory cell region; and

a second dielectric layer disposed between the gate electrode and the substrate and between the gate electrode and the second isolation structure, wherein the second dielectric layer is in direct contact with the second isolation structure.

2. The semiconductor structure according to claim 1 , wherein a groove is formed in the substrate in the capacitor region, and the electrode layer and the first dielectric layer are disposed in the groove.

3. The semiconductor structure according to claim 2 , wherein a width of the groove is greater than or equal to a width of the first isolation structure.

4. The semiconductor structure according to claim 1 , wherein the electrode layer comprises an upper part and a lower part connected to each other, and a width of the upper part is greater than a width of the lower part.

5. The semiconductor structure according to claim 1 , wherein a cross-sectional shape of the electrode layer comprises a T-shape.

6. The semiconductor structure according to claim 1 , wherein a top-view shape of the electrode layer comprises a grid shape.

7. The semiconductor structure according to claim 1 , wherein the second isolation structure defines an active region in the substrate in the memory cell region.

8. The semiconductor structure according to claim 7 , wherein the gate electrode extends over a part of the active region and a part of the second isolation structure.

9. The semiconductor structure according to claim 8 , wherein a depth of the electrode layer is greater than a depth of the gate electrode located directly above the active region.

10. The semiconductor structure according to claim 8 , wherein a depth of the gate electrode located directly above the second isolation structure is greater than a depth of the gate electrode located directly above the active region.

11. A manufacturing method of a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a capacitor region;

forming a first isolation structure in the substrate in the capacitor region; and

forming a capacitor in the capacitor region, wherein the capacitor comprises:

the substrate in the capacitor region;

an electrode layer disposed in the substrate in the capacitor region; and

a first dielectric layer disposed between the electrode layer and the substrate and between the electrode layer and the first isolation structure, wherein the first dielectric layer is in direct contact with the first isolation structure,

wherein the substrate further comprises a memory cell region, and the manufacturing method of the semiconductor structure further comprises:

forming a second isolation structure in the substrate in the memory cell region;

forming a gate electrode in the substrate in the memory cell region; and

forming a second dielectric layer between the gate electrode and the substrate and between the gate electrode and the second isolation structure, wherein the second dielectric layer is in direct contact with the second isolation structure.

12. The manufacturing method of the semiconductor structure according to claim 11 , wherein the electrode layer and the gate electrode are formed simultaneously.

13. The manufacturing method of the semiconductor structure according to claim 11 , wherein a formation method of the electrode layer, the gate electrode, the first dielectric layer and the second dielectric layer comprises:

forming a first isolation material layer in the substrate in the capacitor region, and forming a second isolation material layer in the substrate in the memory cell region;

removing a part of the first isolation material layer, and forming the first isolation structure and a first groove in the substrate in the capacitor region, wherein the first groove is located directly above the first isolation structure;

removing a part of the second isolation material layer and a part of the substrate in the memory cell region, and forming the second isolation structure and a second groove in the substrate in the memory cell region, wherein the second isolation structure defines an active region in the substrate in the memory cell region, and the second groove extends over a part of the active region and a part of the second isolation structure;

forming a dielectric material layer on the substrate, the first isolation structure, the second isolation structure, a surface of the first groove and a surface of the second groove;

forming a conductive material layer on the dielectric material layer, wherein the conductive material layer fills the first groove and the second groove; and

removing the conductive material layer and the dielectric material layer located outside the first groove and outside the second groove to form the electrode layer, the gate electrode, the first dielectric layer and the second dielectric layer.

14. The manufacturing method of the semiconductor structure according to claim 13 , wherein a formation method of the first isolation material layer and the second isolation material layer comprises performing a shallow trench isolation structure manufacturing process.

15. The manufacturing method of the semiconductor structure according to claim 13 , wherein a formation method of the first groove and the second groove comprises:

forming a patterned photoresist layer on the substrate, wherein the patterned photoresist layer exposes the part of the first isolation material layer, and the patterned photoresist layer exposes the part of the substrate in the memory cell region and the part of the second isolation material layer; and

performing a dry etching manufacturing process on the first isolation material layer, the second isolation material layer and the substrate in the memory cell region using the patterned photoresist layer as a mask.

16. The manufacturing method of the semiconductor structure according to claim 15 , wherein, in the dry etching manufacturing process, an etching rate of a material of the first isolation material layer is greater than an etching rate of a material of the substrate in the memory cell region, so that a depth of the first groove is greater than a depth of the second groove located directly above the active region.

17. The manufacturing method of the semiconductor structure according to claim 15 , wherein in the dry etching manufacturing process, an etching rate of a material of the second isolation material layer is greater than an etching rate of a material of the substrate in the memory cell region, so that a depth of the second groove located directly above the second isolation structure is greater than a depth of the second groove located directly above the active region.

18. The manufacturing method of the semiconductor structure according to claim 13 , further comprising:

removing a part of the substrate in the capacitor region in a process of removing the part of the first isolation material layer, so that a width of the first groove is greater than a width of the first isolation structure.