Semiconductor memory device, electronic device and method for setting the same
An electronic device includes a semiconductor memory device configured to store process information and to output the process information to the outside; and a host configured to read the process information from the semiconductor memory device, and to select one of a plurality of operation modes depending on the process information so as to be set to an operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or a response characteristic of the semiconductor memory device.
1. A semiconductor memory device configured to:
provide, to a host, process information indicating whether a process used to manufacture the semiconductor memory device is a legacy process providing first device performance or an enhanced process which provides second device performance higher than the first device performance of the legacy process, the process information being stored in the semiconductor memory device as a part of the process of manufacturing the semiconductor memory device;
receive, from the host, an instruction to set an operation mode of the semiconductor memory device to a target operation mode, the target operation mode being selected, based on the process information, among a plurality of operation modes, and the plurality of operation modes defining a plurality of respectively different latencies, by which data are output from the semiconductor memory device in response to a read command; and
set the operation mode of the semiconductor memory device to the target operation mode,
wherein the plurality of respectively different latencies include a first latency and a second latency, the second latency being longer than the first latency, and
wherein a first operation mode is selected as the target operation mode in response to the process information indicating the enhanced process, and a second operation mode is selected as the target operation mode in response to the process information indicating the legacy process.
2. The semiconductor memory device as claimed in claim 1 ,
wherein the enhanced process corresponds to a high-K metal gate process or a fin field effect transistor process.
3. The semiconductor memory device as claimed in claim 1 ,
wherein each of the first device performance and the second device performance indicates at least one of a voltage level, a clock frequency, and a latency.
4. The semiconductor memory device as claimed in claim 1 ,
wherein the plurality of operation modes include:
a third operation mode, in which the semiconductor memory device is set to operate at a third latency and a first voltage level,
a fourth operation mode, in which the semiconductor memory device is set to operate at the third latency and a second voltage level, the second voltage level being less than the first voltage level, and
a fifth operation mode, in which the semiconductor memory device is set to operate at a fourth latency and the first voltage level, the fourth latency being less than the third latency.
5. The semiconductor memory device as claimed in claim 1 ,
wherein the process information corresponds to the process used to manufacture a peripheral circuit to control a cell array of the semiconductor memory device.
6. The semiconductor memory device as claimed in claim 1 , further comprising a program component configured to store the process information.
7. The semiconductor memory device as claimed in claim 1 ,
wherein the process information is provided through a mode register read by the host.
8. The semiconductor memory device as claimed in claim 1 , further comprising a mode register set configured to indicate at least one of an operating voltage level or an operating speed corresponding to the target operation mode.
9. A host configured to control a semiconductor memory device configured to:
read, from the semiconductor memory device, process information indicating whether a process used to manufacture the semiconductor memory device is a legacy process providing first device performance or an enhanced process which provides second device performance higher than the first device performance of the legacy process, the process information being stored in the semiconductor memory device as a part of the process of manufacturing the semiconductor memory device;
select a target operation mode among a plurality of operation modes depending on the process information; and
set an operation mode of the semiconductor memory device based on the selected target operation mode,
wherein the plurality of operation modes define a plurality of respectively different latencies, by which data are output from the semiconductor memory device in response to a read command,
wherein the plurality of respectively different latencies include a first latency and a second latency, the second latency being longer than the first latency, and
wherein a first operation mode is selected as the target operation mode in response to the process information indicating the enhanced process, and a second operation mode is selected as the target operation mode in response to the process information indicating the legacy process.
10. The host as claimed in claim 9 ,
wherein the enhanced process corresponds to a high-K metal gate process or a fin field effect transistor process.
11. The host as claimed in claim 9 ,
wherein each of the first device performance and the second device performance indicates at least one of a voltage level, a clock frequency, and a latency.
12. The host as claimed in claim 9 ,
wherein the plurality of operation modes include:
a third operation mode, in which the semiconductor memory device is set to operate at a third latency and a first voltage level,
a fourth operation mode, in which the semiconductor memory device is set to operate at the third latency and a second voltage level, the second voltage level being less than the first voltage level, and
a fifth operation mode, in which the semiconductor memory device is set to operate at a fourth latency and the first voltage level, the fourth latency being less than the third latency.
13. The host as claimed in claim 9 ,
wherein the process information corresponds to the process used to manufacture a peripheral circuit to control a cell array of the semiconductor memory device.
14. The host as claimed in claim 9 ,
wherein the process information is read from a mode register of the semiconductor memory device.
15. The host as claimed in claim 9 , wherein, further configured to set the operation mode of the semiconductor memory device with an operation parameter corresponding to the first operation mode in response to the process information corresponding to the enhanced process.
16. The host as claimed in claim 15 , further configured to perform a training operation for optimizing a reference voltage level and a timing of the semiconductor memory device set with the operation parameter.