Sustainable DRAM having principle power supply voltage unified with logic circuit
View Patent ↗This invention discloses sustainable DRAM with principle power supply voltage which is unified with an external logic circuit. The DRAM circuit is configured to couple with the external logic circuit and with a principle power supply voltage source. The DRAM circuit comprises a first sustaining voltage generator and a DRAM core circuit. The first sustaining voltage generator generates a first voltage level which is higher than a voltage level corresponding to a signal ONE utilized in the DRAM circuit. The DRAM core circuit has a DRAM cell comprising an access transistor and a storage capacitor, and the storage capacitor of the DRAM cell is configured to selectively coupled to the first sustaining voltage generator. Wherein, a voltage level of the principle power supply voltage source to the DRAM circuit is the same or substantially the same as that of a principle power supply voltage source to the external logic circuit.
1. A DRAM chip configured to couple with an external logic circuit chip and to couple with a principle power supply voltage source, comprising:
a first sustaining voltage generator producing a first voltage level which is higher than a voltage level corresponding to a signal ONE utilized in the DRAM chip; and
a DRAM core circuit with a DRAM cell comprising an access transistor and a storage capacitor;
wherein the storage capacitor of the DRAM cell is configured to selectively coupled to the first sustaining voltage generator;
wherein a voltage level of the principle power supply voltage source to the DRAM chip is the same or substantially the same as that of a principle power supply voltage source to the external logic circuit chip, wherein the DRAM chip is physically separate from the external logic circuit chip, the DRAM chip and the external logic circuit chip are two different semiconductor chips, and the voltage level of the principle power supply voltage source to the DRAM chip is not greater than 0.9V, wherein during write operation of the signal ONE to the DRAM cell, the storage capacitor is stored the first voltage level, and the voltage level corresponding to the signal ONE utilized in the DRAM chip is equal to the voltage level of the principle power supply voltage source;
wherein a process node of the external logic circuit chip is smaller than that of the DRAM chip.
2. The DRAM chip in claim 1 , further comprising an I/O circuit and a peripheral circuit between the I/O circuit and the DRAM core circuit, wherein an operation supply voltage to a drain side of a transistor in the peripheral circuit is the same as the voltage level of the principle power supply voltage source to the DRAM chip.
3. The DRAM chip in claim 2 , where an operation supply voltage to a drain side of a transistor in the DRAM core circuit which is not the access transistor is the same as the voltage level of the principle power supply voltage source to the DRAM chip.
4. The DRAM chip in claim 3 , where the voltage level corresponding to the signal ONE utilized in the DRAM chip is the same as the voltage level of the principle power supply voltage source to the DRAM chip.
5. The DRAM chip in claim 1 , further comprising an I/O circuit and a peripheral circuit which is between the I/O circuit and the DRAM core circuit, the I/O circuit being without an input comparator circuit and an output level converting circuit.
6. The DRAM chip in claim 1 , wherein the voltage level of the external principle power supply voltage source to the DRAM chip is between 0.9V˜0.5V.
7. The DRAM chip in claim 1 , further comprising a word line coupled to a gate terminal of the access transistor, wherein the word-line is selected to turn on the access transistor for a first period and a second period which is after the first period, and the first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during the second period.
8. The DRAM chip in claim 7 , wherein the first period is an access operation period, and the second period is a restore phase period.
9. The DRAM chip in claim 8 , wherein a kicking charge source is electrically coupled to a bit line of the DRAM chip during the access operation period.
10. A DRAM chip configured to couple with an external logic circuit chip and with a principle power supply voltage source, comprising:
a DRAM core circuit with a DRAM cell comprising an access transistor and a storage capacitor;
an I/O circuit configured to couple to the external logic circuit chip and being without an input comparator circuit and an output level converting circuit; and
a peripheral circuit between the I/O circuit and the DRAM core circuit;
wherein a voltage level of the principle power supply voltage source to the DRAM chip is the same or substantially the same as that of a principle power supply voltage source to the external logic circuit chip, the voltage level of the principle power supply voltage source to the DRAM chip is not greater than 0.9V, and the DRAM chip is physically separate from the logic circuit chip;
wherein the DRAM chip and the external logic circuit chip are two different semiconductor chips, and a process node of the external logic circuit chip is smaller than that of the DRAM chip;
wherein during write operation of a signal ONE to the DRAM cell, the storage capacitor is stored a first voltage level generated by a first sustaining voltage generator comprised in the DRAM chip, the first voltage level is higher than a voltage level corresponding to the signal ONE utilized in the DRAM chip, and the voltage level corresponding to the signal ONE utilized in the DRAM chip is equal to the voltage level of the principle power supply voltage source.
11. The DRAM chip in claim 10 , wherein an operation supply voltage to a drain side of a transistor in the peripheral circuit is the same as the voltage level of the principle power supply voltage source to the DRAM chip.
12. The DRAM chip in claim 11 , where an operation supply voltage to a drain side of a transistor in the DRAM core circuit which is not the access transistor is the same as the voltage level of the principle power supply voltage source to the DRAM chip.
13. The DRAM chip in claim 12 , where the voltage level corresponding to the signal ONE utilized in the DRAM chip is the same as the voltage level of the principle power supply voltage source to the DRAM chip.
14. The DRAM chip in claim 10 , further comprising:
a first sustaining voltage generator producing a first voltage level which is higher than a voltage level corresponding to a signal ONE utilized in the DRAM chip; and
a word line coupled to a gate terminal of the access transistor, wherein the word-line is selected to turn on the access transistor for a first period and a second period which is after the first period, and the first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during the second period.
15. The DRAM chip in claim 14 , wherein the first period is an access operation period, the second period is a restore phase period.
16. A memory system, comprising:
a DRAM chip, comprising:
a DRAM core circuit with a DRAM cell comprising an access transistor and a storage capacitor; and
an I/O circuit without an input comparator circuit and an output level converting circuit; and
a logic circuit chip electrically coupled to the DRAM chip, wherein the DRAM chip is physically separate from the logic circuit chip;
wherein a voltage level of a principle power supply voltage source to the DRAM chip is the same or substantially the same as that of a principle power supply voltage source to the logic chip; wherein a voltage level of the principle power supply voltage source to the DRAM chip is not greater than 0.9V;
wherein the DRAM chip and the external logic circuit chip are two different semiconductor chips, and a process node of the external logic circuit chip is smaller than that of the DRAM chip;
wherein during write operation of a signal ONE to the DRAM cell, the storage capacitor is stored a first voltage level generated by a first sustaining voltage generator comprised in the DRAM chip, the first voltage level is higher than a voltage level corresponding to the signal ONE utilized in the DRAM chip, and the voltage level corresponding to the signal ONE utilized in the DRAM chip is equal to the voltage level of the principle power supply voltage source.
17. The memory system in claim 16 , wherein the DRAM chip includes a DRAM circuit, the logic circuit chip includes a logic circuit and a physical layer circuit; wherein the principle power supply voltage source to the DRAM chip is supplied to the DRAM circuit, and the principle power supply voltage source to the logic circuit chip is supplied to the logic circuit and the physical layer circuit.
18. The memory system in claim 16 , further comprising a based chip electrically coupled to the DRAM chip; wherein the voltage level of the principle power supply voltage source to the DRAM chip is the same or substantially the same as that of a principle power supply voltage source to the based chip.
19. The memory system in claim 18 , wherein the DRAM chip includes a DRAM circuit, the logic circuit chip includes a logic circuit, and the based chip includes a physical layer circuit; wherein the principle power supply voltage source to the DRAM chip is supplied to the DRAM circuit, the principle power supply voltage source to the logic circuit chip is supplied to the logic circuit, and the principle power supply voltage source to the based chip is supplied to the physical layer circuit.
20. The memory system in claim 16 , the DRAM chip comprising a DRAM cell and a first sustaining voltage generator, the DRAM cell comprising a storage capacitor and an access transistor, and the first sustaining voltage generator producing a first voltage level which is higher than a voltage level corresponding to a signal ONE utilized in the DRAM chip; wherein the first sustaining voltage generator is coupled to the storage capacitor of the DRAM cell before the access transistor of the DRAM cell is turned off.
21. The memory system in claim 20 , the DRAM chip further comprising a peripheral circuit between the I/O circuit and the DRAM cell.
22. The memory system in claim 16 , further comprising a physical layer circuit with an I/O physical circuit, and the I/O physical circuit being without an input comparator circuit and an output level converting circuit.