Granted Patent B2

US 12,346,488 · App. 17/697,203 · Granted Jul 1, 2025

Inventor: Gregory R. Conti (St. Paul, FR)

Assignee: TEXAS INSTRUMENTS INCORPORATED

G06F21/85

Abstract

Claims (79)

1. A system comprising:

a target;

an interconnect coupled to the target;

a direct memory access (DMA) subsystem coupled to the interconnect, wherein the DMA subsystem includes an internal register and a DMA channel, wherein the DMA channel is operable to make a transaction to transfer information to the target via the interconnect, wherein the internal register is operable to specify a plurality of qualifiers, and wherein a first qualifier of the plurality of qualifiers designates whether the transaction is a secure mode transaction or a normal mode transaction; and

an initiator coupled to the DMA subsystem,

wherein the initiator is operable to:

issue a DMA request to the DMA subsystem to cause the DMA subsystem to make the transaction; and

issue an access request to the DMA subsystem to configure the internal register.

2. The system of claim 1 , wherein a second qualifier of the plurality of qualifiers designates whether the transaction is a data transaction or an instruction transaction.

3. The system of claim 2 , wherein a third qualifier of the plurality of qualifiers designates whether the transaction is a privilege mode transaction or a public mode transaction.

4. The system of claim 3 , wherein a fourth qualifier of the plurality of qualifiers designates whether the transaction is a functional mode transaction or a debug mode transaction.

5. The system of claim 1 ,

wherein the internal register is accessible only when the access request to the DMA subsystem is a secure mode access request, and

wherein at least a first part of the internal register is configurable to specify the first qualifier.

6. The system of claim 5 , further comprising a processor,

wherein the DMA subsystem is configurable to detect a security violation based on the access request, and

wherein the DMA subsystem is configurable to cause an interrupt to the processor in response to detecting the security violation.

7. The system of claim 6 , wherein the DMA subsystem is further configurable to send an error response to the initiator in response to detecting the security violation.

8. The system of claim 5 ,

wherein the internal register further includes a second part configurable to specify a second qualifier of the plurality of qualifiers, and

wherein the second qualifier designates whether the transaction is a data transaction or an instruction transaction.

9. The system of claim 8 ,

wherein the internal register further includes a third part configurable to specify a third qualifier of the plurality of qualifiers, and

wherein the third qualifier designates whether the transaction is a privilege mode transaction or a public mode transaction.

10. The system of claim 9 ,

wherein the internal register comprises a DMA rights register including the first part, the second part, and the third part, and

wherein the first part, the second part, the third part are configurable all at once by one access request issued by the initiator.

11. The system of claim 9 ,

wherein the internal register further includes a fourth part configurable to specify a fourth qualifier of the plurality of qualifiers, and

wherein the fourth qualifier designates whether the transaction is a functional mode transaction or a debug mode transaction.

12. The system of claim 1 , wherein the DMA subsystem comprises a firewall configurable to:

receive a fifth qualifier with the access request from the initiator; and

in response to receiving the fifth qualifier, configure the DMA channel for read operations and write operations.

13. The system of claim 12 , wherein the fifth qualifier comprises an MReqSecure bit in the access request.

14. The system of claim 1 , wherein the DMA subsystem comprises a firewall configurable to:

receive the access request from the initiator;

determine that the access request includes no qualifiers; and

in response to determining that the access request includes no qualifiers, configure the DMA channel for only read operations.

15. The system of claim 1 , wherein the access request comprises an Open Core Protocol access request.

16. The system of claim 1 , wherein the initiator comprises a digital signal processor.

17. The system of claim 1 , wherein the target comprises a synchronous dynamic random-access memory scheduler.

18. A method comprising:

receiving, by a direct memory access (DMA) subsystem coupled to an interconnect, a DMA request from an initiator;

making, by a DMA channel of the DMA subsystem, a transaction to transfer information to a target via the interconnect in response to the DMA request, wherein an internal register of the DMA subsystem specifies a plurality of qualifiers, and wherein a first qualifier of the plurality of qualifiers designates whether the transaction is a secure mode transaction or a normal mode transaction; and

receiving, by the DMA subsystem from the initiator, an access request to configure the internal register.

19. The method of claim 18 , further comprising providing access to the internal register only when the access request is a secure mode access request,

wherein at least a first part of the internal register is configurable to specify the first qualifier.

20. The method of claim 19 , further comprising:

detecting a security violation based on the access request; and

sending an interrupt to a processor in response to detecting the security violation.

21. The method of claim 20 , further comprising sending an error response to the initiator in response to detecting the security violation.

22. The method of claim 19 ,

wherein the internal register further includes a second part configurable to specify a second qualifier of the plurality of qualifiers,

wherein the second qualifier designates whether the transaction is a data transaction or an instruction transaction,

wherein the internal register further includes a third part configurable to specify a third qualifier of the plurality of qualifiers,

wherein the third qualifier designates whether the transaction is a privilege mode transaction or a public mode transaction,

wherein the internal register comprises a DMA rights register including the first part, the second part, and the third part, and

wherein the method further comprises configuring the first part, the second part, the third part all at once in response to receiving the access request from the initiator.

23. The method of claim 18 , further comprising:

receiving a fifth qualifier with the access request from the initiator; and

in response to receiving the fifth qualifier, configure the DMA channel for read operations and write operations.

24. The method of claim 18 , further comprising:

receiving the access request from the initiator;

determining that the access request includes no qualifiers; and

in response to determining that the access request includes no qualifiers, configuring the DMA channel for only read operations.

25. A system comprising:

a target;

an interconnect coupled to the target;

an internal register including a first part, a second part, and a third part, wherein the first part is configurable to specify a first qualifier of a plurality of qualifiers, wherein the second part is configurable to specify a second qualifier of the plurality of qualifiers, and wherein the third part is configurable to specify a third qualifier of the plurality of qualifiers;

a direct memory access (DMA) channel coupled to the interconnect, wherein the DMA channel is configurable to make a transaction to transfer information to the target via the interconnect, and wherein the first qualifier designates whether the transaction is a secure mode transaction or a normal mode transaction;

a first initiator configurable to:

issue a DMA request to cause the DMA channel to make the transaction; and

issue a first access request to configure the internal register;

a second initiator configurable to issue a second access request to configure the internal register; and

a firewall configurable to:

receive a fourth qualifier with the first access request from the first initiator;

in response to receiving the fourth qualifier, configure the DMA channel for read operations and write operations;

determine that the second access request includes no qualifiers; and

in response to determining that the second access request includes no qualifiers, configure the DMA channel for only read operations.

Priority Claims (1)

Continuity (3)

References Cited (27)