Systems and methods for safely subscribing to locks using hardware extensions
Transactional Lock Elision allows hardware transactions to execute unmodified critical sections protected by the same lock concurrently, by subscribing to the lock and verifying that it is available before committing the transaction. A “lazy subscription” optimization, which delays lock subscription, can potentially cause behavior that cannot occur when the critical sections are executed under the lock. Hardware extensions may provide mechanisms to ensure that lazy subscriptions are safe (e.g., that they result in correct behavior). Prior to executing a critical section transactionally, its lock and subscription code may be identified (e.g., by writing their locations to special registers). Prior to committing the transaction, the thread executing the critical section may verify that the correct lock was correctly subscribed to. If not, or if locations identified by the special registers have been modified, the transaction may be aborted. Nested critical sections associated with different lock types may invoke different subscription code.
1. A system, comprising:
one or more processor cores; and
a memory coupled to the one or more processor cores and storing program instructions that when executed on the one or more processor cores cause the one or more processor cores to execute a multithreaded application that comprises a critical section, wherein the critical section is associated with a lock, and wherein a thread of the multithreaded application is configured to:
store information identifying the lock in a lock address register; and
execute the critical section using a hardware transaction, wherein to execute the critical section the thread is configured to:
subscribe, within the hardware transaction, to a boolean register associated with the lock, wherein to subscribe to the boolean register the thread is configured to:
determine, according to the boolean register, whether another critical section associated with the lock is currently being executed; and
in response to determining that said other critical section associated with the lock is not currently being executed and the lock address register has not been modified during execution of the hardware transaction, commit the hardware transaction.
2. The system of claim 1 , wherein the thread of the multithreaded application is further configured to abort the hardware transaction in response to determining that another critical section associated with the lock is currently being executed or the lock address register has been modified during execution of the hardware transaction.
3. The system of claim 1 , wherein the information identifying the lock comprises a location of the boolean register residing in a hardware transactional memory.
4. The system of claim 3 , wherein subscribing to the boolean register is performed in response to encountering, during execution of the critical section using the hardware transaction, an instruction that signals an end of the critical section, and wherein to subscribe to the boolean register the thread is further configured to:
read a value from the location identified by the information; and
determine, dependent on the value read from the location, whether another critical section associated with the lock is currently being executed.
5. The system of claim 1 , wherein the thread of the multithreaded application is further configured to:
enter, immediately prior to subscribing to the boolean register, a special mode in which attempts to execute code in the write set of the hardware transaction and attempts to read data in the write set of the hardware transaction are disallowed; and
abort the hardware transaction in response to an attempt by the thread to execute code that is in the write set of the hardware transaction while in the special mode, in response to an attempt by the thread to read data that is in the write set of the hardware transaction while in the special mode, or in response to another thread acquiring the lock.
6. A computer implemented method, comprising:
performing, by a thread of a multi-threaded application executing on a computer that supports multithreading:
storing information identifying a lock in a lock address register; and
executing a critical section using a hardware transaction, comprising:
subscribing, within the hardware transaction, to a boolean register associated with the lock, comprising:
determining, according to the boolean register, whether another critical section protected by the lock is currently being executed; and
in response to determining that said other critical section protected by the lock is not currently being executed and the lock address register has not been modified during execution of the hardware transaction, committing the hardware transaction.
7. The system of claim 1 , wherein a protected memory area of a given size comprises:
the lock address register storing a value identifying a location at which the lock associated with the critical section resides in a hardware transactional memory; and
wherein the one or more processor cores are configured to abort the hardware transaction in response to an attempt, during execution of the hardware transaction, to reduce the size of the protected memory area.
8. The system of claim 6 , wherein the multithreaded application comprises two or more critical sections including the critical section and the other critical section.
9. The computer implemented method of claim 6 , the thread further performing aborting the hardware transaction in response to determining that another critical section protected by the lock is currently being executed or the lock address register has been modified during execution of the hardware transaction.
10. The computer implemented method of claim 6 , wherein the information identifying the lock comprises a location of the boolean register residing in a hardware transactional memory.
11. The computer implemented method of claim 10 , wherein subscribing to the boolean register is performed in response to encountering, during execution of the critical section using the hardware transaction, an instruction that signals an end of the critical section, and wherein subscribing to the boolean register comprises:
reading a value from the location identified by the information; and
determining, dependent on the value read from the location, whether another critical section protected by the lock is currently being executed.
12. The computer implemented method of claim 6 , the thread further performing:
entering, immediately prior to subscribing to the boolean register, a special mode in which attempts to execute code in the write set of the hardware transaction and attempts to read data in the write set of the hardware transaction are disallowed; and
aborting the hardware transaction in response to an attempt by the thread to execute code that is in the write set of the hardware transaction while in the special mode, in response to an attempt by the thread to read data that is in the write set of the hardware transaction while in the special mode, or in response to another thread acquiring the lock.
13. The computer implemented method of claim 6 , wherein the multithreaded application comprises two or more critical sections including the critical section and the other critical section.
14. The computer implemented method of claim 6 , wherein a protected memory area of a given size comprises:
the lock address register storing a value identifying a location at which the lock associated with the critical section resides in a hardware transactional memory; and
wherein the one or more processor cores are configured to abort the hardware transaction in response to an attempt, during execution of the hardware transaction, to reduce the size of the protected memory area.
15. One or more non-transitory computer-readable storage media storing program instructions that when executed on or across one or more computers cause the one or more computers to implement a thread of a multi-threaded application to perform:
storing information identifying a lock in a lock address register; and
executing a critical section using a hardware transaction, comprising:
subscribing, within the hardware transaction, to a boolean register associated with the lock, comprising:
determining, according to the boolean register, whether another critical section protected by the lock is currently being executed; and
in response to determining that said other critical section protected by the lock is not currently being executed and the lock address register has not been modified during execution of the hardware transaction, committing the hardware transaction.
16. The one or more non-transitory, computer-readable storage media of claim 15 , the thread further performing aborting the hardware transaction in response to determining that another critical section protected by the lock is currently being executed or the lock address register has been modified during execution of the hardware transaction.
17. The one or more non-transitory, computer-readable storage media of claim 15 , wherein the information identifying the lock comprises a location of the boolean register residing in a hardware transactional memory.
18. The one or more non-transitory, computer-readable storage media of claim 17 , wherein subscribing to the boolean register is performed in response to encountering, during execution of the critical section using the hardware transaction, an instruction that signals an end of the critical section, and wherein subscribing to the boolean register comprises:
reading a value from the location identified by the information; and
determining, dependent on the value read from the location, whether another critical section protected by the lock is currently being executed.
19. The one or more non-transitory, computer-readable storage media of claim 15 , the thread further performing:
entering, immediately prior to subscribing to the boolean register, a special mode in which attempts to execute code in the write set of the hardware transaction and attempts to read data in the write set of the hardware transaction are disallowed; and
aborting the hardware transaction in response to an attempt by the thread to execute code that is in the write set of the hardware transaction while in the special mode, in response to an attempt by the thread to read data that is in the write set of the hardware transaction while in the special mode, or in response to another thread acquiring the lock.
20. The one or more non-transitory, computer-readable storage media of claim 15 , wherein the multithreaded application comprises two or more critical sections including the critical section and the other critical section.