Semiconductor device transistor having multiple channels with different widths and materials
Embodiments of the present disclosure provide a semiconductor device structure including a first channel layer formed of a first material, wherein the first channel layer has a first width, a second channel layer formed of a second material different from the first material, wherein the second channel layer has a second width less than the first width, and the second channel layer is in contact with a first surface of the first channel layer. The structure also includes a third channel layer formed of the second material, wherein the third channel layer has a third width less than the second width, and the third channel layer is in contact with a second surface of the first channel layer. The structure also includes a gate dielectric layer conformally disposed on the first channel layer, the second channel layer, and the third channel layer, and a gate electrode layer disposed on the gate dielectric layer.
1. A semiconductor device structure, comprising:
a first channel layer formed of a first material, wherein the first channel layer has a first width;
a second channel layer formed of a second material different from the first material, wherein the second channel layer has a second width less than the first width, and the second channel layer is in contact with a first surface of the first channel layer;
a third channel layer formed of the second material, wherein the third channel layer has a third width less than the second width, and the third channel layer is in contact with a second surface of the first channel layer;
a gate dielectric layer conformally disposed on the first channel layer, the second channel layer, and the third channel layer; and
a gate electrode layer disposed on the gate dielectric layer.
2. The semiconductor device structure of claim 1 , wherein the second channel layer has a height that is greater than the second width.
3. The semiconductor device structure of claim 1 , further comprising:
a fourth channel layer formed of the first material, wherein the fourth channel layer has a fourth width substantially similar to the first width, and the fourth channel layer is in contact with the second channel layer.
4. The semiconductor device structure of claim 3 , further comprising:
a fifth channel layer formed of the first material, wherein the fifth channel layer has a fifth width substantially similar to the first width, and the fifth channel layer is in contact with the third channel layer.
5. The semiconductor device structure of claim 4 , wherein the second material of the second channel layer has a first germanium atomic percentage range, and the second material of the third channel layer has a second germanium atomic percentage range greater than the first germanium atomic percentage range.
6. The semiconductor device structure of claim 4 , wherein the gate dielectric layer is further disposed on the fourth channel layer and the fifth channel layer.
7. The semiconductor device structure of claim 4 , wherein the second channel layer has a first portion having a first diameter and a second portion having a second diameter that is less than the first diameter.
8. A semiconductor device structure, comprising:
a plurality of first channel layers formed of a first material, wherein each of the plurality of the first channel layer has a first width and a first surface profile;
two or more second channel layers interposed between and in contact with the plurality of the first channel layers, wherein each of the two or more second channel layers has a width less than the first width, and each of the two or more second channel layers has a second surface profile that is different than the first surface profile;
a gate dielectric layer conformally disposed over and wrapping each of the plurality of the first channel layers and each of the two or more second channel layers, and at least a surface of the first channel layer is in contact with the second channel layer and the gate dielectric layer; and
a gate electrode layer disposed over the gate dielectric layer.
9. The semiconductor device structure of claim 8 , wherein the two or more second channel layers are formed of a second material different from the first material.
10. The semiconductor device structure of claim 9 , wherein the first material comprises silicon, and the second material comprises germanium.
11. The semiconductor device structure of claim 8 , wherein each of the two or more second channel layers has a height that is greater than the width of each of the two or more second channel layers.
12. The semiconductor device structure of claim 8 , wherein the first surface profile is substantially flat and the second surface profile has a tapered shape.
13. The semiconductor device structure of claim 8 , wherein the second channel layer at an upper elevation has a first diameter, the second channel layer at a middle elevation has a second diameter, and the second channel layer at a lower elevation has a third diameter that is smaller than the first diameter and the second diameter.
14. The semiconductor device structure of claim 13 , wherein the first diameter and the second diameter are substantially the same.
15. The semiconductor device structure of claim 13 , wherein the second channel layer at the upper and middle elevations has a first germanium atomic percentage range, and the second material at the lower elevation has a second germanium atomic percentage range greater than the first germanium atomic percentage range.
16. A semiconductor device structure, comprising:
a first channel layer formed of a first material, wherein the first channel layer has a first width;
a second channel layer formed of the first material, wherein the second channel layer has a second width corresponding to the first width;
a third channel layer formed of a second material different from the first material, wherein the second channel layer comprises:
a first portion in contact with the first channel layer;
a second portion opposing the first portion and in contact with the second channel layer, the first and second portions having a third width less than the first width; and
a third portion interposed between and in contact with the first portion and the second portion, wherein the third portion has a fourth width less than the third width;
a gate dielectric layer conformally disposed over the first, second, and third channel layers; and
a gate electrode layer disposed over the gate dielectric layer.
17. The semiconductor device structure of claim 16 , wherein the third channel layer has a height that is greater than the third and fourth widths.
18. The semiconductor device structure of claim 17 , wherein the first and second portions have a taper shape and the third portion has a flat surface.
19. The semiconductor device structure of claim 17 , further comprising:
a fourth channel layer formed of the second material and in contact with the second channel layer, wherein the fourth channel layer has a fifth width less than the third width.
20. The semiconductor device structure of claim 19 , wherein the second material of the third channel layer has a first germanium atomic percentage range, and the second material of the fourth channel layer has a second germanium atomic percentage range greater than the first germanium atomic percentage range.