Thin film transistors having semiconductor structures integrated with 2D channel materials
Thin film transistors having semiconductor structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is above the 2D material layer, the gate stack having a first side opposite a second side. A semiconductor structure including germanium is included, the semiconductor structure laterally adjacent to and in contact with the 2D material layer adjacent the first side of the gate stack. A first conductive structure is adjacent the first side of the second gate stack, the first conductive structure over and in direct electrical contact with the semiconductor structure. The semiconductor structure is intervening between the first conductive structure and the 2D material layer. A second conductive structure is adjacent the second side of the second gate stack, the second conductive structure over and in direct electrical contact with the 2D material layer.
1. An integrated circuit structure, comprising:
a two-dimensional (2D) material layer above a substrate;
a gate stack above the 2D material layer, the gate stack having a first side opposite a second side;
a semiconductor structure comprising germanium, the semiconductor structure laterally adjacent to and in contact with the 2D material layer adjacent the first side of the gate stack;
a first conductive structure adjacent the first side of the gate stack, the first conductive structure over and in direct electrical contact with the semiconductor structure, wherein the semiconductor structure is intervening between the first conductive structure and the 2D material layer; and
a second conductive structure adjacent the second side of the gate stack, the second conductive structure over and in direct electrical contact with the 2D material layer.
2. The integrated circuit structure of claim 1 , wherein the semiconductor structure extends from a location below the 2D material layer to a location above the 2D material layer.
3. The integrated circuit structure of claim 1 , wherein the semiconductor structure is a P-type semiconductor structure.
4. The integrated circuit structure of claim 1 , wherein the gate stack comprises a high-k gate dielectric layer directly on the 2D material layer.
5. The integrated circuit structure of claim 1 , wherein the 2D material layer comprises a sulfide material selected from the group consisting of molybdenum sulfide (MoS 2 ) and tungsten sulfide (WS 2 ).
6. The integrated circuit structure of claim 1 , wherein the 2D material layer comprises a selenide material selected from the group consisting of molybdenum selenide (MoSe 2 ), tungsten selenide (WSe 2 ), and indium selenide (InSe), or comprises MoTe 2 .
7. An integrated circuit structure, comprising:
a transition metal dichalcogenide (TMD) channel layer on an insulator layer on a silicon substrate;
a gate stack above the TMD channel layer, the gate stack having a first side opposite a second side, and the gate stack including a high-k gate dielectric layer directly on the TMD channel layer;
a structure comprising germanium and boron, the structure laterally adjacent to and in contact with the TMD channel layer adjacent the first side of the gate stack, the structure in a cavity in the insulator layer, and the structure on an N+ doped region of the silicon substrate;
a source structure adjacent the first side of the gate stack, the source structure over and in direct electrical contact with the structure comprising germanium and boron, but not in direct electrical contact with the TMD channel layer; and
a drain structure adjacent the second side of the gate stack, the drain structure over and in direct electrical contact with the TMD channel layer.
8. The integrated circuit structure of claim 7 , wherein the structure comprising germanium and boron extends from a location below the TMD channel layer to a location above the TMD channel layer.
9. The integrated circuit structure of claim 7 , wherein the TMD channel layer comprises a sulfide material selected from the group consisting of molybdenum sulfide (MoS 2 ) and tungsten sulfide (WS 2 ).
10. The integrated circuit structure of claim 7 , wherein the TMD channel layer comprises a selenide material selected from the group consisting of molybdenum selenide (MoSe 2 ), tungsten selenide (WSe 2 ), and indium selenide (InSe), or comprises MoTe 2 .
11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a two-dimensional (2D) material layer above a substrate;
a gate stack above the 2D material layer, the gate stack having a first side opposite a second side;
a semiconductor structure comprising germanium, the semiconductor structure laterally adjacent to and in contact with the 2D material layer adjacent the first side of the gate stack;
a first conductive structure adjacent the first side of the gate stack, the first conductive structure over and in direct electrical contact with the semiconductor structure, wherein the semiconductor structure is intervening between the first conductive structure and the 2D material layer; and
a second conductive structure adjacent the second side of the gate stack, the second conductive structure over and in direct electrical contact with the 2D material layer.
12. The computing device of claim 11 , further comprising:
a memory coupled to the board.
13. The computing device of claim 11 , further comprising:
a communication chip coupled to the board.
14. The computing device of claim 11 , further comprising:
a camera coupled to the board.
15. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
16. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a transition metal dichalcogenide (TMD) channel layer on an insulator layer on a silicon substrate;
a gate stack above the TMD channel layer, the gate stack having a first side opposite a second side, and the gate stack including high-k gate dielectric layer directly on the TMD channel layer;
a structure comprising germanium and boron, the structure laterally adjacent to and in contact with the TMD channel layer adjacent the first side of the gate stack, the structure in a cavity in the insulator layer, and the structure on an N+ doped region of the silicon substrate;
a source structure adjacent the first side of the gate stack, the source structure over and in direct electrical contact with the structure, but not in direct electrical contact with the TMD channel layer; and
a drain structure adjacent the second side of the gate stack, the drain structure over and in direct electrical contact with the TMD channel layer.
17. The computing device of claim 16 , further comprising:
a memory coupled to the board.
18. The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19. The computing device of claim 16 , further comprising:
a camera coupled to the board.
20. The computing device of claim 16 , wherein the component is a packaged integrated circuit die.