IP Library › Granted Patent US 12,349,461
Granted Patent B2
US 12,349,461 · App. 17/894,712 · Granted Jul 1, 2025

Transfer printing for RF applications

Inventors: Imène Lahbib (Corbeil-Essonnes, FR); Jérôme Loraine (Corbeil-Essonnes, FR); Frédéric Drillet (Corbeil-Essonnes, FR); Albert Kumar (Corbeil-Essonnes, FR); Gregory U'Ren (Corbeil-Essonnes, FR)
Assignee: X-FAB France SAS
H10D86/201H03F3/193H10D62/8503
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Quick Facts
Patent No.
US 12,349,461
App. No.
17/894,712
Granted
Jul 1, 2025
Kind
B2
Abstract

A semiconductor structure for RF applications comprises: a first μTP GaN transistor on an SOI wafer or die; and a first resistor connected to the gate of said first transistor.

Claims (13)

1. A semiconductor structure for amplifying an RF signal comprising:

a cascode structure comprising a μTP GaN transistor on an SOI wafer or die,

wherein said cascode structure further comprises:

an SOI transistor formed on the SOI wafer or die and connected to said μTP GaN transistor; or

a second μTP GaN transistor on the SOI wafer or die and connected to said μTP GaN transistor.

2. A semiconductor structure according to claim 1 , further comprising an inductor connected to a source of said μTP GaN transistor.

3. A semiconductor structure according to claim 1 , further comprising a linearizer formed on the SOI wafer.

4. A semiconductor structure for amplifying an RF signal comprising:

a first LNA on an SOI wafer, wherein said first LNA comprises a cascode structure comprising a first and a second transistor in series and wherein said first or second transistor is a SOI transistor formed on the SOI wafer; and

a second LNA on the SOI wafer connected to said first LNA, wherein said second LNA comprises a μTP GaN transistor.

5. A semiconductor structure according to claim 4 , wherein said first LNA comprises a μTP GaN transistor.

6. A semiconductor structure according to claim 4 , further comprising one or more further LNAs on the SOI wafer connected together so as to amplify an RF signal applied to said first LNA when in use.

7. A semiconductor structure according to claim 4 , wherein the first and second LNAs are powered by the same power supply.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2022
From: LAHBIB, IMÈNE; LORAINE, JÉRÔME; DRILLET, FRÉDÉRIC; KUMAR, ALBERT; U'REN, GREGORY
To: X-FAB FRANCE SAS
Reel/Frame 060896/0722 →
Priority Claims (1)
FR 1904958 · May 13, 2019 · national
Continuity (2)
Division 16866902 · May 5, 2020
Related Publication 20220415927A1 · Dec 29, 2022
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