Capacitance measurement circuit
A capacitance measurement circuit includes an analog front-end (AFE) circuit with current mirror circuits, a parasitic capacitor, an AD converter, an output shift register, and a controller. The controller disconnects a capacitor to be measured and connects one current mirror circuit to record an AFE output voltage V N collected at an inverting input terminal of the AD converter, then connects the capacitor to be measured to collect an AFE output voltage V P at a non-inverting input terminal of the AD converter, and converts a value of (V P −V N ) into a first digital signal; determines, based on the value of the first digital signal, a connection number m of the current mirror circuits, controls the analog front-end circuit to connect m current mirror circuits, and repeat the steps to obtain a second digital signal; and shift the second digital signal based on the connection number m to obtain a capacitance measurement value.
1. A capacitance measurement circuit, comprising: an analog front-end circuit, a parasitic capacitor, an analog to digital converter (ADC), an output shift register, and a controller;
wherein input terminals of the ADC are connected to an output terminal of the analog front-end circuit, and an output terminal of the ADC is connected to the output shift register;
wherein an input terminal of the analog front-end circuit is connected to the parasitic capacitor and a capacitor to be measured individually; the analog front-end circuit comprises M numbers of current mirror circuits connected in parallel, where M=2 N−1 and N is a positive integer;
wherein the controller is configured to control the analog front-end circuit, the parasitic capacitor, the ADC, and the output shift register to measure the capacitor to be measured, specifically to:
step 1, control one of the current mirror circuits of the analog front-end circuit to be turned on;
step 2, disconnect the capacitor to be measured, and control an inverting input terminal of the ADC to continuously collect analog front end (AFE) output voltages of the analog front-end circuit before connection of the capacitor to be measured;
step 3, control the analog front-end circuit to charge the parasitic capacitor to a first reference voltage, and record an AFE output voltage V N currently collected at the inverting input terminal of the ADC;
step 4, connect the capacitor to be measured, after the analog front-end circuit is stabilized, control a non-inverting input terminal of the ADC to collect an AFE output voltage V P of the analog front-end circuit, and control the ADC to convert a difference value (V P −V N ) of the AFE output voltage V P and the AFE output voltage V N into a first digital signal;
step 5, determine, based on a value of the first digital signal, a connection number m of the current mirror circuits, and control the m numbers of current mirror circuits of the analog front-end circuit to be turned on; where m=2 n−1 and n is a positive integer less than or equal to N; and
step 6, repeat the step 2 to step 4 to obtain a second digital signal, and control, based on the connection number m, the output shift register to shift the second digital signal to obtain a capacitance measurement value of the capacitor to be measured.
2. The capacitance measurement circuit according to claim 1 , wherein after the step 5, the first digital signal is taken as the capacitance measurement value of the capacitor to be measured when a value of the connection number m is 1.
3. The capacitance measurement circuit according to claim 1 , wherein in the step 5, the determine, based on a value of the first digital signal, a connection number m of the current mirror circuits, specifically comprises:
the connection number m is 1 when the value of the first digital signal is greater than D max /2; where D max is a maximum output value of the ADC;
the connection number m is 2 when the value of the first digital signal is less than D max /2 and greater than D max /8;
the connection number m is 2 i−1 when the value of the first digital signal is less than D max /2 i and greater than D max /2 i+1 ; where i is a positive integer greater than or equal to 3.
4. The capacitance measurement circuit according to claim 3 , wherein in the step S 6 , the control, based on the connection number m, the output shift register to shift the second digital signal to obtain a capacitance measurement value of the capacitor to be measured, specifically comprises:
control, in response to the value of the connection number m being 1, the output shift register to not shift the second digital signal to obtain the capacitance measurement value of the capacitor to be measured;
control, in response to the value of the connection number m being 2, the output shift register to shift the second digital signal by one bit to right to obtain the capacitance measurement value of the capacitor to be measured;
control, in response to the value of the connection number m being 2 i−1 , the output shift register to shift the second digital signal to the right by i−1 bits to obtain the capacitance measurement value of the capacitor to be measured.
5. The capacitance measurement circuit according to claim 1 , wherein the analog front-end circuit comprises an operational amplifier, a first capacitor, a second capacitor, a voltage follower, and the M numbers of current mirror circuits connected in parallel;
wherein each of the current mirror circuits comprises two current mirror sub-circuits with a width to length ratio of 1:1 and a reverser arranged between the two current mirror sub-circuits;
wherein a non-inverting input terminal of the operational amplifier is connected to the input terminal of the analog front-end circuit, an inverting input terminal of the operational amplifier is connected to a first end of the first capacitor, and an output terminal of the operational amplifier is connected to the M numbers of current mirror circuits connected in parallel;
wherein an input terminal of the voltage follower is individually connected to a first end of the second capacitor and the M numbers of current mirror circuits connected in parallel, and an output terminal of the voltage follower is connected to the output terminal of the analog front-end circuit; and
wherein a second end of the first capacitor and a second end of the second capacitor each are connected to a signal ground.
6. The capacitance measurement circuit according to claim 5 , wherein the input terminal of the analog front-end circuit is connected to the capacitor to be measured, specifically:
the input terminal of the analog front-end circuit is connected to the capacitor to be measured through a control switch S 3 ;
the controller is further configured to control the control switch S 3 to switch on to thereby control the connection of the capacitor to be measured, or control the control switch S 3 to switch off to thereby control the disconnection of the capacitor to be measured.
7. The capacitance measurement circuit according to claim 5 ,
wherein the input terminals of the ADC are connected to the output terminal of the analog front-end circuit, specifically:
the inverting input terminal of the ADC is connected to the output terminal of the analog front-end circuit through a control switch S 4 , and the non-inverting input terminal of the ADC is connected to the output terminal of the analog front-end circuit;
the controller is further configured to control the control switch S 4 to switch on to thereby control connection of the inverting input terminal of the ADC, or control the control switch S 4 to switch off to thereby control disconnection of the inverting input terminal of the ADC.