Granted Patent B2

US 12,353,813 · App. 17/883,357 · Granted Jul 8, 2025

Inventor: Tetsuhisa Mido (Tokyo, JP)

Assignee: Synopsys, Inc.

G06F30/367G06F30/20G06F30/3308G06F30/398

Abstract

Claims (36)

1. A method for circuit analysis, comprising:

removing noise from an edge response of a circuit to produce a modified edge response;

performing superposition of the modified edge response to generate a waveform;

adding the removed noise to the waveform to generate a noised waveform; and

generating, based on the noised waveform, an eye diagram for the circuit.

2. The method of claim 1 , wherein the noise comprises steady-state noise.

3. The method of claim 1 , wherein the noise is independent of data input for the circuit.

4. The method of claim 1 , wherein the noise is determined with a logic low representation of signals of the circuit.

5. The method of claim 1 , wherein the noise is determined based on a first noise waveform determined using a logic low representation of signals of the circuit and a second noise waveform determined using a logic high representation of the signals of the circuit.

6. The method of claim 5 , wherein the noise is determined based on a weighted average of the first noise waveform and the second noise waveform.

7. The method of claim 1 , wherein the noise comprises noise induced by a power supply for the circuit.

8. The method of claim 1 , wherein the noise comprises noise induced by crosstalk between communication channels in the circuit.

9. The method of claim 1 , further comprising verifying an operation of the circuit based on the eye diagram.

10. A system for circuit analysis, comprising:

a memory; and

a processor communicatively coupled to the memory, the processor configured to:

remove noise from an edge response of a circuit to produce a modified edge response;

perform superposition of the modified edge response to generate a waveform;

add the removed noise to the waveform to generate a noised waveform; and

generate, based on the noised waveform, an eye diagram for the circuit.

11. The system of claim 10 , wherein the noise comprises steady-state noise.

12. The system of claim 10 , wherein the noise is independent of data input for the circuit.

13. The system of claim 10 , wherein the noise is determined with a logic low representation of signals of the circuit.

14. The system of claim 10 , wherein the noise is determined based on a first noise waveform determined using a logic low representation of signals of the circuit and a second noise waveform determined using a logic high representation of the signals of the circuit.

15. The system of claim 14 , wherein the noise is determined based on a weighted average of the first noise waveform and the second noise waveform.

16. The system of claim 10 , wherein the noise comprises noise induced by a power supply for the circuit.

17. The system of claim 10 , wherein the noise comprises noise induced by crosstalk between communication channels in the circuit.

18. The system of claim 10 , wherein the processor is further configured to verify an operation of the circuit based on the eye diagram.

19. A non-transitory computer readable medium storing instructions that, when executed by a processor, cause the processor to:

characterize a steady-state noise in a circuit induced by a power supply for the circuit;

remove the steady-state noise from an edge response of the circuit to produce a modified edge response;

generate a waveform by performing superposition of the modified edge response;

add the steady-state noise to the waveform to generate a noised waveform;

generate, based on the noised waveform, an eye diagram for the circuit; and

verify an operation of the circuit based on the eye diagram.

20. The medium of claim 19 , wherein adding the steady-state noise to the waveform comprises convoluting the steady-state noise with the waveform.

Assignments (1)

Continuity (2)

References Cited (19)