Memory system for performing an erase voltage application operation and an erase verify operation for a nonvolatile memory
According to an embodiment, a memory system includes: a nonvolatile memory including a plurality of blocks; and a memory controller. The memory controller is configured to: make a comparison between a first erase voltage application accumulated time period and a first erase verify permission time period each corresponding to a first block targeted for erasure; cause the nonvolatile memory to execute a erase voltage application operation in a case where the first erase voltage application accumulated time period is less than the first erase verify permission time period; and cause the nonvolatile memory to execute a erase verify operation in a case where the first erase voltage application accumulated time period is equal to or greater than the first erase verify permission time period.
1. A memory system comprising:
a nonvolatile memory including a plurality of blocks each including a plurality of memory cells and being a unit of erasure; and
circuitry programmed to transmit a first command set for an erase voltage application operation and a second command set for an erase verify operation to the nonvolatile memory, to erase data in at least one of the blocks,
wherein the circuitry is programmed to:
select a first block targeted for erasure from the plurality of blocks;
make a comparison between a first erase voltage application accumulated time period and a first erase verify permission time period each corresponding to the first block;
transmit the first command set to the nonvolatile memory to execute the erase voltage application operation in a case where the first erase voltage application accumulated time period is less than the first erase verify permission time period; and
transmit the second command set to the nonvolatile memory to execute the erase verify operation in a case where the first erase voltage application accumulated time period is equal to or greater than the first erase verify permission time period, and
the nonvolatile memory is programmed to execute the erase voltage application operation based on the first command set and to execute the erase verify operation based on the second command set.
2. The memory system according to claim 1 , wherein the first command set for the erase voltage application operation includes an erase voltage application set time period.
3. The memory system according to claim 2 , wherein the circuitry is programmed to determine the erase voltage application set time period based on a difference between a first erase voltage application target time period corresponding to the first block and the first erase voltage application accumulated time period.
4. The memory system according to claim 1 , wherein the circuitry includes a timer and is programmed to:
calculate an erase voltage application time period based on a measurement value of the timer after termination of the erase voltage application operation; and
add the erase voltage application time period to the first erase voltage application accumulated time period.
5. The memory system according to claim 4 , wherein the timer measures a time period during which a first signal received from the nonvolatile memory in execution of the erase voltage application operation is at a first logical level.
6. The memory system according to claim 1 , wherein the circuitry is programmed to:
further select a second block targeted for erasure from the plurality of blocks;
make a comparison between a second erase voltage application accumulated time period and a second erase verify permission time period each corresponding to the second block; and
transmit the first command set to the nonvolatile memory to execute the erase voltage application operation targeted for the first block and the second block in a case where the first erase voltage application accumulated time period is less than the first erase verify permission time period and the second erase voltage application accumulated time period is less than the second erase verify permission time period.
7. The memory system according to claim 6 , wherein the nonvolatile memory further includes:
a first plane including the first block and a first row decoder coupled to the first block; and
a second plane including the second block and a second row decoder coupled to the second block.
8. The memory system according to claim 6 , wherein the nonvolatile memory further includes a first plane including the first block, the second block, and a first row decoder coupled to the first block and the second block.
9. The memory system according to claim 6 , wherein in a case of causing the nonvolatile memory to execute the erase voltage application operation targeted for the first block and the second block, the circuitry is programmed to:
determine an erase voltage application set time period based on smaller one of a difference between a first erase voltage application target time period and the first erase voltage application accumulated time period corresponding to the first block and a difference between a second erase voltage application target time period and the second erase voltage application accumulated time period corresponding to the second block; and
issue the first command set for the erase voltage application operation, including the erase voltage application set time period.
10. The memory system according to claim 1 , wherein in a case where the erase verify operation on the first block indicates a failure, the circuitry is programmed to:
update the first erase voltage application accumulated time period to an initial value; and
transmit the first command set to the nonvolatile memory to execute the erase voltage application operation on the first block after updating the first erase voltage application accumulated time period.
11. The memory system according to claim 10 , wherein in a case where the erase verify operation on the first block indicates a failure, the circuitry is programmed to:
update erase voltage application set information; and
transmit the first command set to the nonvolatile memory to execute the erase voltage application operation on the first block after updating the erase voltage application set information.
12. The memory system according to claim 1 , wherein the circuitry is programmed to:
further select a second block targeted for erasure from the plurality of blocks;
make a comparison between first erase voltage application set information on the first block and second erase voltage application set information on the second block;
in a case where the first erase voltage application set information and the second erase voltage application set information are different from each other, select one of the first block and the second block; and
in a case where the first erase voltage application set information and the second erase voltage application set information are identical to each other, select the first block and the second block in a batch.
13. The memory system according to claim 1 ,
wherein the first block further includes a plurality of string units each including the plurality of memory cells, and
the circuitry is programmed to select at least one of first string units targeted for the erase verify operation from the plurality of string units in the erase verify operation.
14. The memory system according to claim 13 , wherein in a case where the circuitry selects one of the first string units, the second command set for the erase verify operation includes an address of the selected one of the first string units.
15. The memory system according to claim 13 , wherein in a case where the circuitry selects a plurality of the first string units, the second command set for the erase verify operation includes an address of one of the first string units from which the erase verify operation is initiated and information on a number of the selected first string units.
16. The memory system according to claim 13 , wherein in a case where the erase verify operation indicates a pass, the circuitry is programmed to store information on a string unit which has passed the erase verify operation.
17. The memory system according to claim 1 , wherein upon termination of the erase verify operation, the circuitry is programmed to read information based on a result of the erase verify operation from the nonvolatile memory.