Methods of etching metals in semiconductor devices
A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.
1. A method, comprising:
forming a first metal layer over a semiconductor substrate;
forming a second metal layer directly on the first metal layer, wherein a composition of the second metal layer is different from a composition of the first metal layer;
forming a metal-containing hard mask layer over the second metal layer;
patterning the metal-containing hard mask layer;
etching the second metal layer using the patterned metal-containing hard mask layer as an etch mask to form a conductive line, wherein the etched second metal layer exposes a portion of the first metal layer;
treating the exposed portion of the first metal layer with a plasma; and
removing both the patterned metal-containing hard mask layer and the treated exposed portion of the first metal layer in a wet etching process.
2. The method of claim 1 , wherein forming the first metal layer includes depositing a first metal including copper, chromium, ruthenium, titanium, vanadium, palladium, indium, or combinations thereof.
3. The method of claim 1 , wherein forming the second metal layer includes forming a second metal including molybdenum, osmium, iridium, cobalt, niobium, platinum, rhodium, rhenium, or combinations thereof.
4. The method of claim 1 , wherein forming the metal-containing hard mask layer includes depositing a metal-containing layer including titanium nitride, tantalum nitride, or a combination thereof.
5. The method of claim 1 , wherein the patterning of the metal-containing hard mask layer includes etching the metal-containing hard mask layer with a fluorine-free plasma, and wherein etching the second metal layer includes applying a fluorine-containing plasma.
6. The method of claim 1 , wherein the treating the exposed portion of the first metal layer with the plasma includes applying an inert gas to form a porous first metal layer.
7. The method of claim 1 , further comprising
forming a via in a first dielectric layer disposed over the semiconductor substrate, wherein the forming of the first metal layer over the semiconductor substrate includes forming the first metal layer over the first dielectric layer, and wherein the removing both the patterned metal-containing hard mask layer and the treated exposed portion of the first metal layer in the wet etching process includes exposing the first dielectric layer; and
forming a second dielectric layer over the exposed first dielectric layer.
8. The method of claim 1 , wherein the removing both the patterned metal-containing hard mask layer and the treated exposed portion of the first metal layer includes applying an etchant that includes peroxide (H 2 O 2 ), sulfuric acid (H 2 SO 4 ), hydrofluoric acid (HF), hydrochloric acid (HCl), vinylhydroperoxide (CH 2 CHOOH), phosphoric acid (H 3 PO 4 ), nitric acid (HNO 3 ), ammonia (NH 3 ), deionized water (DI H 2 O), or combinations thereof.
9. The method of claim 1 , wherein the etching the second metal layer includes implements a plasma that is free of any chlorine-containing gas.
10. The method of claim 9 , wherein the etching the second metal layer includes applying an etchant that includes a bromine-containing gas, a nitrogen-containing gas, an oxygen-containing gas, a hydrogen-containing gas, a carbon-containing gas, or combinations thereof.
11. The method of claim 1 , prior to the forming a first metal layer, further comprising
forming a via in a first dielectric layer disposed over the semiconductor substrate; and
forming an etch-stop layer (ESL) between the via and the first metal layer, and wherein sidewalls of the ESL are defined by the first dielectric layer.
12. A method, comprising:
forming a first metal layer over a via in a first interlayer dielectric (ILD) layer disposed over a semiconductor substrate, the first metal layer including a first metal;
forming a second metal layer over the first ILD layer, wherein the second metal layer includes a second metal different from the first metal;
forming a third metal layer over the second metal layer, wherein the third metal layer includes a third metal different from the second metal;
forming a patterned hard mask layer over the third metal layer;
performing a first dry etching process using a first etchant to the third metal layer through the patterned hard mask layer, thereby forming a conductive feature adjacent to a trench, wherein the trench exposes a portion of the second metal layer;
performing a second dry etching process to the second metal layer through the patterned hard mask layer using a second etchant different from the first etchant; and
performing a wet etching process to remove the patterned hard mask layer, thereby extending the trench to expose a portion of the first ILD layer.
13. The method of claim 12 , wherein the forming the third metal layer includes forming the third metal layer directly on the second metal layer.
14. The method of claim 13 , further comprising forming a second ILD layer to fill the trench, wherein sidewalls of the first metal layer are defined by the first ILD layer, and wherein the first metal layer includes a first metal.
15. The method of claim 12 , wherein forming the first metal layer includes:
patterning the first ILD layer to form a via opening;
partially filling the via opening to form the via, wherein a top surface of the via is lower than a top surface of the first ILD layer;
forming the first metal layer over the via, wherein a portion of the first metal layer is formed over the top surface of the first ILD layer; and
planarizing the first metal layer to expose the top surface of the first ILD layer.
16. The method of claim 12 , wherein
the second metal includes copper, chromium, ruthenium, titanium, vanadium, palladium, indium, or combinations thereof; and
the third metal includes molybdenum, osmium, iridium, cobalt, niobium, platinum, rhodium, rhenium, or combinations thereof.
17. The method of claim 12 , wherein
the performing the first dry etching process includes implementing a fluorine-containing etchant; and
the performing the second dry etching process includes implementing a fluorine-free etchant.
18. The method of claim 17 , wherein the forming the patterned hard mask layer includes:
depositing a metal-containing hard mask layer over the third metal layer; and
performing a third dry etching process to pattern the metal-containing hard mask layer using an etchant that is a fluorine-free etchant.
19. A method, comprising:
forming a first metal layer over a via in a first interlayer dielectric (ILD) layer disposed over a semiconductor substrate, the first metal layer including a first metal;
forming a second metal layer over the first ILD layer, wherein the second metal layer includes a second metal different from the first metal;
forming a third metal layer directly on the second metal layer, wherein the third metal layer includes a third metal different from the second metal;
forming a patterned metal-containing hard mask layer over the third metal layer;
performing a first dry etching process using a fluorine-containing etchant to the third metal layer through the patterned metal-containing hard mask layer, thereby forming a conductive feature adjacent to a trench, wherein the trench exposes a portion of the second metal layer;
performing a second dry etching process to the second metal layer through the patterned hard mask layer using a fluorine-free etchant; and
performing a wet etching process to remove the patterned hard mask layer, thereby extending the trench to expose a portion of the first ILD layer.
20. The method of claim 19 , wherein
the second metal includes copper, chromium, ruthenium, titanium, vanadium, palladium, indium, or combinations thereof; and
the third metal includes molybdenum, osmium, iridium, cobalt, niobium, platinum, rhodium, rhenium, or combinations thereof.