IP Library › Granted Patent US 12,356,620
Granted Patent B2
US 12,356,620 · App. 17/887,766 · Granted Jul 8, 2025

Semiconductor device and method for manufacturing same

Inventors: Junichi Kaneyama (Yokkaichi Mie, JP); Keiichi Sawa (Yokkaichi Mie, JP); Hiroyuki Yamashita (Yokkaichi Mie, JP)
Assignee: KIOXIA CORPORATION
H10B43/27H10D64/037H10D64/685
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Quick Facts
Patent No.
US 12,356,620
App. No.
17/887,766
Granted
Jul 8, 2025
Kind
B2
Abstract

A semiconductor device includes a plurality of electrode layers separated from each other in a first direction, a charge storage layer provided on side surfaces of the plurality of electrode layers via a first insulating film, and a semiconductor layer provided on a side surface of the charge storage layer via a second insulating film. The charge storage layer includes a location having a fluorine concentration of 5.0×10 18 atoms/cm 3 or less. A fluorine concentration at an interface between the charge storage layer and the second insulating film is 10 times or more or 1/10 or less of a fluorine concentration at an interface between the charge storage layer and the first insulating film.

Claims (62)

1. A semiconductor device comprising:

a plurality of electrode layers separated from each other in a first direction;

a charge storage layer disposed on side surfaces of the plurality of electrode layers via a first insulating film; and

a semiconductor layer disposed on a side surface of the charge storage layer via a second insulating film, wherein

the charge storage layer includes a portion having a fluorine concentration of 5.0×10 18 atoms/cm 3 or less, and

a fluorine concentration at an interface between the charge storage layer and the second insulating film is 10 times or more, or 1/10 or less, that of a fluorine concentration at an interface between the charge storage layer and the first insulating film.

2. The semiconductor device according to claim 1 , wherein

the fluorine concentration at the interface between the charge storage layer and the first insulating film is 5.0×10 18 atoms/cm 3 or less, and

the fluorine concentration at the interface between the charge storage layer and the second insulating film is 5.0×10 19 atoms/cm 3 or more.

3. The semiconductor device according to claim 1 , wherein

the second insulating film includes a location having a fluorine concentration of 1.0×10 19 atoms/cm 3 or more and 1.0×10 20 atoms/cm 3 or less.

4. The semiconductor device according to claim 1 , wherein

the fluorine concentration at the interface between the charge storage layer and the first insulating film is 5.0×10 19 atoms/cm 3 or more, and

the fluorine concentration at the interface between the charge storage layer and the second insulating film is 5.0×10 18 atoms/cm 3 or less.

5. The semiconductor device according to claim 1 , wherein

the fluorine concentration in the charge storage layer (i) increases from the first insulating film to a predetermined location, and (ii) decreases from the predetermined location to the second insulating film, along a second direction from the first insulating film to the second insulating film.

6. The semiconductor device according to claim 1 , wherein the charge storage layer includes:

a first region having a first fluorine concentration, and

a second region provided on the second insulating film side with respect to the first region, the second region having a second fluorine concentration higher than the first fluorine concentration.

7. The semiconductor device according to claim 6 , wherein

the first fluorine concentration is 5.0×10 18 atoms/cm 3 or less, and

the second fluorine concentration is 5.0×10 19 atoms/cm 3 or more.

8. The semiconductor device according to claim 1 , wherein

the fluorine concentration in the charge storage layer increases from the first insulating film to the second insulating film along a second direction from the first insulating film to the second insulating film.

9. The semiconductor device according to claim 1 , wherein

the fluorine concentration in the charge storage layer and the second insulating film has a peak in the second insulating film.

10. The semiconductor device according to claim 1 , wherein

the fluorine concentration in the charge storage layer and the second insulating film has a peak at the interface between the charge storage layer and the second insulating film.

11. The semiconductor device according to claim 1 , wherein

a film thickness of a first portion of the charge storage layer is thicker than 1 nm or more of a film thickness of a second portion of the charge storage layer.

12. The semiconductor device according to claim 11 , further comprising:

a plurality of memory cells, wherein

the first portion of the charge storage layer is disposed outside the memory cell, and

the second portion of the charge storage layer is disposed in the memory cell.

13. A semiconductor device comprising:

a plurality of electrode layers separated from each other in a first direction;

a charge storage layer disposed on side surfaces of the plurality of electrode layers via a first insulating film; and

a semiconductor layer disposed on a side surface of the charge storage layer via a second insulating film, wherein

the charge storage layer includes a portion having a fluorine concentration of 5.0×10 18 atoms/cm 3 or less, and

a maximum value of a fluorine concentration in the charge storage layer is 10 times or more a minimum value of a fluorine concentration in the charge storage layer.

14. The semiconductor device according to claim 13 , wherein

a fluorine concentration at an interface between the charge storage layer and the second insulating film is 10 times or more or 1/10 or less of a fluorine concentration at an interface between the charge storage layer and the first insulating film.

15. A method for manufacturing a semiconductor device comprising:

forming a plurality of first layers separated from each other in a first direction;

forming a charge storage layer on side surfaces of the plurality of first layers via a first insulating film;

forming a semiconductor layer on a side surface of the charge storage layer via a second insulating film;

removing the plurality of first layers to form a plurality of first recess portions; and

forming a plurality of electrode layers in the plurality of first recess portions, wherein

a fluorine concentration in a portion of the charge storage layer has a fluorine concentration of 5.0×10 18 atoms/cm 3 or less, and

a fluorine concentration at an interface between the charge storage layer and the second insulating film is set to be 10 times or more, or 1/10 or less, of a fluorine concentration at an interface between the charge storage layer and the first insulating film.

16. The method for manufacturing the semiconductor device according to claim 15 , further comprising:

performing annealing in an atmosphere containing nitrogen and oxygen between formation of the first recess portion and formation of the electrode layer.

17. The method for manufacturing the semiconductor device according to claim 16 , wherein

the annealing reduces the fluorine concentration in the charge storage layer, and the fluorine concentration in the portion of the charge storage layer is 5.0×10 18 atoms/cm 3 or less.

18. The method for manufacturing the semiconductor device according to claim 16 , further comprising:

forming a third insulating film in the first recess portion between the formation of the first recess portion and the formation of the electrode layer, wherein

the annealing is performed before forming the third insulating film.

19. The method for manufacturing the semiconductor device according to claim 16 , further comprising:

forming a third insulating film in the first recess portion between the formation of the first recess portion and the formation of the electrode layer, wherein

the annealing is performed after forming the third insulating film.

20. The method for manufacturing the semiconductor device according to claim 15 , wherein

a film thickness of a first portion of the charge storage layer is at least 1 nm thicker than a film thickness of a second portion of the charge storage layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2022
From: KANEYAMA, JUNICHI; SAWA, KEIICHI; YAMASHITA, HIROYUKI
To: KIOXIA CORPORATION
Reel/Frame 060903/0692 →
Priority Claims (1)
JP 2021-191334 · Nov 25, 2021 · national
Continuity (1)
Related Publication 20230164998A1 · May 25, 2023
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