Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device includes the steps of providing a substrate having a first region and a second region, forming a first fin-shaped structure on the first region, removing part of the first fin-shaped structure to form a first trench, forming a dielectric layer in the first trench to form a double diffusion break (DDB) structure, forming a first gate structure and a second gate structure on the DDB structure as a bottom surface of the first gate structure is lower than a top surface of the first fin-shaped structure, and forming a contact plug between the first gate structure and the second gate structure on the DDB structure.
1. A method for fabricating semiconductor device, comprising:
providing a substrate having a first region and a second region;
forming a first fin-shaped structure on the first region;
removing part of the first fin-shaped structure to form a first trench;
forming a dielectric layer in the first trench to form a double diffusion break (DDB) structure;
forming a first gate structure and a second gate structure on the DDB structure, wherein a bottom surface of the first gate structure is lower than a top surface of the first fin-shaped structure; and
forming a contact plug between the first gate structure and the second gate structure and directly on the DDB structure.
2. The method of claim 1 , further comprising:
forming the first fin-shaped structure on the first region and a second fin-shaped structure on the second region;
removing part of the first fin-shaped structure and part of the second fin-shaped structure to form the first trench and a second trench;
forming the DDB structure in the first trench and a single diffusion break (SDB) structure in the second trench;
forming the first gate structure and the second gate structure on the DDB structure and a third gate structure on the SDB structure.
3. The method of claim 2 , wherein a bottom surface of the third gate structure is lower than a top surface of the second fin-shaped structure.
4. The method of claim 2 , further comprising:
forming a first source/drain region adjacent to the first gate structure and the second gate structure and a second source/drain region adjacent to the third gate structure; and
performing a replacement metal gate (RMG) process to transform the first gate structure, the second gate structure, and the third gate structure into a first metal gate, a second metal gate, and a third metal gate.
5. The method of claim 2 , wherein the step of forming the first gate structure and the second gate structure comprises:
forming a gate material layer on the DDB structure; and
patterning the gate material layer to form the first gate structure, the second gate structure, and the third gate structure.
6. The method of claim 5 , further comprising performing a sidewall image transfer (SIT) process for patterning the gate material layer.
7. The method of claim 2 , wherein a width of the first gate structure is equal to a width of the third gate structure.
8. The method of claim 1 , wherein the first gate structure overlaps the first fin-shaped structure and the DDB structure.
9. The method of claim 1 , wherein the second gate structure overlaps the first fin-shaped structure and the DDB structure.
10. The method of claim 1 , wherein a width of the first gate structure is equal to a width of the second gate structure.
11. The method of claim 1 , wherein the first region comprises a NMOS region and the second region comprises a PMOS region.
12. A semiconductor device, comprising:
a substrate having a first region and a second region;
a first fin-shaped structure on the first region;
a double diffusion break (DDB) structure in the first fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion;
a first gate structure and a second gate structure on the DDB structure, wherein a bottom surface of the first gate structure is lower than a top surface of the first fin-shaped structure; and
a contact plug between the first gate structure and the second gate structure and directly on the DDB structure.
13. The semiconductor device of claim 12 , wherein the first gate structure overlaps the first portion and the DDB structure.
14. The semiconductor device of claim 12 , wherein the second gate structure overlaps the second portion and the DDB structure.
15. The semiconductor device of claim 12 , further comprising:
a second fin-shaped structure on the second region;
a single diffusion break (SDB) structure in the second fin-shaped structure to divide the second fin-shaped structure into a third portion and a fourth portion; and
a third gate structure on the SDB structure.
16. The semiconductor device of claim 15 , wherein a bottom surface of the third gate structure is lower than a top surface of the second fin-shaped structure.
17. The semiconductor device of claim 15 , wherein the third gate structure overlaps the third portion, the fourth portion, and the SDB structure.
18. The semiconductor device of claim 15 , wherein a width of the first gate structure is equal to a width of the third gate structure.
19. The semiconductor device of claim 12 , wherein a width of the first gate structure is equal to a width of the second gate structure.
20. The semiconductor device of claim 12 , wherein the first region comprises a NMOS region and the second region comprises a PMOS region.