Transistor configurations for vertical memory arrays
Methods, systems, and devices for transistor configurations for vertical memory arrays are described. A memory device may implement a multi-transistor architecture, such as a two-transistor architecture, that is operable to couple pillars with bit lines. For example, a memory device may include a conductive pillar that extends through levels of a memory array. The pillar may be coupled with a first bit line via a first transistor and coupled with a second bit line via a second transistor. To access a memory cell coupled with the pillar, the memory device may bias a word line coupled with the memory cell to a first access voltage, bias one of the bit lines to a second access voltage, activate one of the transistors to couple the pillar with the one of the bit lines, and deactivate the other transistor to isolate the pillar from the other of the bit lines.
1. A memory device, comprising:
a conductive pillar extending through a plurality of levels of a memory array, wherein, at each level of the plurality of levels, one or more memory cells of the memory array are coupled between the conductive pillar and a respective word line;
a first transistor operable to couple the conductive pillar with a first bit line while the first bit line is biased with a negative voltage; and
a second transistor operable to couple the conductive pillar with a second bit line while the second bit line is biased with a positive voltage.
2. The memory device of claim 1 , wherein each of the memory cells comprises a chalcogenide material.
3. The memory device of claim 1 , wherein:
the first transistor is an n-type transistor; and
the second transistor is a p-type transistor.
4. The memory device of claim 1 , wherein:
the first transistor is operable to couple the conductive pillar with the first bit line based at least in part on a gate of the first transistor being biased with a third voltage and the first bit line being biased with a ground negative voltage; and
the second transistor is operable to couple the conductive pillar with the second bit line based at least in part on a gate of the second transistor being biased with a fourth voltage and the second bit line being biased with the positive voltage.
5. The memory device of claim 4 , wherein the third voltage and the fourth voltage are a same voltage.
6. The memory device of claim 4 , wherein the third voltage and the fourth voltage are a ground voltage.
7. The memory device of claim 4 , wherein:
the first transistor is operable to isolate the conductive pillar from the first bit line while the conductive pillar is coupled with the second bit line based at least in part on the gate of the first transistor being biased with a fifth voltage and the first bit line being biased with an idle voltage; and
the second transistor is operable to isolate the conductive pillar from the second bit line while the conductive pillar is coupled with the first bit line based at least in part on a gate of the second transistor being biased with a sixth voltage and the second bit line being biased with the idle voltage.
8. The memory device of claim 7 , wherein the idle voltage is a ground voltage.
9. The memory device of claim 7 , wherein the fifth voltage is equal to the sixth voltage.
10. The memory device of claim 7 , wherein the fifth voltage and the sixth voltage are equal to a ground voltage.
11. A memory device, comprising:
a conductive pillar;
a word line;
a memory cell coupled between the conductive pillar and the word line; and
circuitry configured cause the memory device to:
perform an access operation on the memory cell, wherein during the access operation on the memory cell, the circuitry is configured to cause the memory device to:
bias the word line with a first voltage;
couple the conductive pillar with a first bit line while the first bit line is biased with a second voltage; and
isolate the conductive pillar from a second bit line while the second bit line is biased with a third voltage between the first voltage and the second voltage.
12. The memory device of claim 11 , wherein:
the first voltage is a positive voltage;
the second voltage is a negative voltage; and
the third voltage is a ground voltage.
13. The memory device of claim 11 , wherein:
to couple the conductive pillar with the first bit line during the access operation, the circuitry is configured to cause the memory device to bias a gate of a first transistor between the conductive pillar and the first bit line with a first gate voltage that is greater than the second voltage; and
to isolate the conductive pillar from the second bit line during the access operation, the circuitry is configured to cause the memory device to bias a gate of a second transistor between the conductive pillar and the second bit line with a second gate voltage that is less than the first voltage.
14. The memory device of claim 13 , wherein the first gate voltage is equal to the second gate voltage.
15. The memory device of claim 11 , further comprising:
a second word line; and
a second memory cell coupled between the conductive pillar and the second word line,
wherein, during the access operation, the circuitry is further configured to cause the memory device to:
bias the second word line with the third voltage.
16. The memory device of claim 11 , further comprising:
a second conductive pillar; and
a third memory cell coupled between the second conductive pillar and the word line,
wherein, during the access operation, the circuitry is further configured to cause the memory device to:
isolate the second conductive pillar from the first bit line based at least in part on biasing a gate of a third transistor between the second conductive pillar and the first bit line with the second voltage; and
isolate the second conductive pillar from the second bit line based at least in part on biasing a gate of a fourth transistor between the second conductive pillar and the second bit line with the first voltage.
17. The memory device of claim 11 , wherein the circuitry is further configured to cause the memory device to:
perform a second access operation on the memory cell, wherein, during the second access operation on the memory cell, the circuitry is configured to cause the memory device to:
bias the word line with the second voltage;
couple the conductive pillar with the second bit line while the second bit line is biased with the first voltage; and
isolate the conductive pillar from the first bit line while the first bit line is biased with the third voltage.
18. The memory device of claim 11 , wherein, during the access operation, the circuitry is configured to cause the memory device to:
determine whether the memory cell thresholds in response to the word line being biased with the first voltage and the first bit line being biased with the second voltage while the conductive pillar is coupled with the first bit line; and
read a logic state of the memory cell based at least in part on determining whether the memory cell thresholds.
19. The memory device of claim 11 , wherein the circuitry is further configured to cause the memory device to:
write the memory cell with a first logic state based at least in part on the word line being biased with the first voltage and the first bit line being biased with the second voltage while the conductive pillar is coupled with the first bit line.
20. A method of operating a memory device, comprising:
accessing a memory cell that is coupled between a conductive pillar of a memory die and a word line of the memory die, the accessing the memory cell comprising:
biasing the word line with a first voltage;
coupling the conductive pillar with a first bit line while the first bit line is biased with a second voltage; and
isolating the conductive pillar from a second bit line while the second bit line is biased with a third voltage between the first voltage and the second voltage.