Granted Patent B2

US 12,361,266 · App. 16/990,970 · Granted Jul 15, 2025

Inventors: Jong Hoon Shin (San Jose, CA); Ali Shafiee Ardestani (San Jose, CA); Hamzah Ahmed Ali Abdelaziz (San Jose, CA); Joseph H. Hassoun (Los Gatos, CA)

Assignee: Samsung Electronics Co., Ltd.

G06N3/06G06F17/16G06N3/0464G06N3/063G06N3/08G06N7/04G06N20/00

Abstract

Claims (67)

1. A method, comprising:

performing intra-tile preprocessing of a first weight tensor to form a first pre-processed weight tensor,

performing inter-tile preprocessing of the first pre-processed weight tensor, to form a second pre-processed weight tensor,

performing, by a processing circuit, a first computation cycle on a first row of the second pre-processed weight tensor,

skipping, by the processing circuit, a second row of the second pre-processed weight tensor based on the intra-tile preprocessing and the inter-tile preprocessing, and

performing, by the processing circuit, a second computation cycle on a third row of the second pre-processed weight tensor in place of the second row of the second pre-processed weight tensor,

such that the first row of the second pre-processed weight tensor and the third row of the second pre-processed weight tensor are processed in two computation cycles, instead of three computational cycles,

the intra-tile preprocessing comprising causing a first row of a first weight tile of the first weight tensor to be empty by moving a first element of the first weight tile of the first weight tensor by one position, within the first weight tile, in a lookahead direction or in a lookaside direction, and

the inter-tile preprocessing comprising causing the second row of the second pre-processed weight tensor to be empty by moving a second row of a first weight tile of the first pre-processed weight tensor by one position, in a lookahead direction or by one position in a lookaside direction, based on a second row of a second weight tile of the first pre-processed weight tensor being empty.

2. The method of claim 1 , wherein the intra-tile preprocessing comprises moving the first element of the first weight tile of the first weight tensor by one position, within the first weight tile, in the lookahead direction.

3. The method of claim 1 , wherein the inter-tile preprocessing comprises moving the second row by one position in a lookahead direction.

4. The method of claim 1 , wherein the intra-tile preprocessing further comprises moving a first element of a second weight tile of the first weight tensor by one position, within the second weight tile, in a lookaside direction.

5. The method of claim 1 , wherein

the inter-tile preprocessing comprises moving a second row of the second weight tile to the first weight tile, in a lookaside direction.

6. The method of claim 5 , wherein the inter-tile preprocessing further comprises creating a tile sparsity map corresponding to the first pre-processed weight tensor, the tile sparsity map having:

a column for each weight tile of the first pre-processed weight tensor, and

a row for each row of the weight tiles,

the tile sparsity map indicating positions of empty rows of the weight tiles of the first pre-processed weight tensor.

7. The method of claim 6 , wherein the tile sparsity map has one fewer dimension than the first pre-processed weight tensor.

8. The method of claim 6 , further comprising identifying the first row of the first weight tile based on the tile sparsity map.

9. The method of claim 6 , further comprising:

multiplying a third row of the first weight tile by a first vector of activations, to form a first dot product,

wherein the multiplying comprises fetching the first vector of activations from a column of an activations buffer, the column of the activations buffer being second in the activations buffer.

10. The method of claim 6 , further comprising:

multiplying, in a first processing element circuit, a third row of the first weight tile by a first vector of activations, to form a first dot product,

multiplying, in a second processing element circuit, a third row of weights, of the first pre-processed weight tensor, by a second vector of activations, to form a second dot product, and

adding the first dot product and the second dot product.

11. The method of claim 6 , wherein the inter-tile preprocessing further comprises moving a third row of the first pre-processed weight tensor by one position in a lookahead direction.

12. The method of claim 11 , further comprising identifying the third row based on the tile sparsity map.

13. A system, comprising:

a first processing circuit, the first processing circuit being configured to:

perform intra-tile preprocessing of a first weight tensor to form a first pre-processed weight tensor,

perform inter-tile preprocessing of the first pre-processed weight tensor, to form a second pre-processed weight tensor,

perform a first computation cycle on a first row of the second pre-processed weight tensor,

skip a second row of the second pre-processed weight tensor based on the intra-tile preprocessing and the inter-tile preprocessing, and

perform a second computation cycle on a third row of the second pre-processed weight tensor in place of the second row of the second pre-processed weight tensor,

such that the first row of the second pre-processed weight tensor and the third row of the second pre-processed weight tensor are processed in two computation cycles, instead of three computational cycles,

the intra-tile preprocessing comprising causing a first row of a first weight tile of the first weight tensor to be empty by moving a first element of the first weight tile of the first weight tensor by one position, within the first weight tile, in a lookahead direction or in a lookaside direction, and

the inter-tile preprocessing comprising causing the second row of the second pre-processed weight tensor to be empty by moving a second row of a first weight tile of the first pre-processed weight tensor by one position, in a lookahead direction or by one position in a lookaside direction, based on a second row of a second weight tile of the first pre-processed weight tensor being empty.

14. The system of claim 13 , wherein the intra-tile preprocessing comprises moving the first element of the first weight tile of the first weight tensor by one position, within the first weight tile, in the lookahead direction.

15. The system of claim 13 , wherein the inter-tile preprocessing comprises moving the second row by one position in a lookahead direction.

16. The system of claim 13 , wherein the intra-tile preprocessing further comprises moving a first element of a second weight tile of the first weight tensor by one position, within the second weight tile, in a lookaside direction.

17. The system of claim 13 , wherein

the inter-tile preprocessing comprises moving a second row of the second weight tile to the first weight tile, in a lookaside direction.

18. The system of claim 17 , wherein the inter-tile preprocessing further comprises creating a tile sparsity map corresponding to the first pre-processed weight tensor, the tile sparsity map having:

a column for each weight tile of the first pre-processed weight tensor, and

a row for each row of the weight tiles,

the tile sparsity map indicating positions of empty rows of the weight tiles of the first pre-processed weight tensor.

19. The system of claim 18 , further comprising a second processing circuit comprising:

a first processing element circuit, and

a second processing element circuit,

wherein:

the first processing element circuit is configured to multiply a third row of the first weight tile by a first vector of activations, to form a first dot product; and

the second processing element circuit is configured to:

multiply a fourth row of weights, of the first pre-processed weight tensor, by a second vector of activations, to form a second dot product, and

add the first dot product and the second dot product.

20. A system, comprising:

a processing circuit; and

a memory communicatively coupled to the processing circuit, the memory storing instructions, which, based on being executed by the processing circuit, cause the processing circuit to:

perform intra-tile preprocessing of a first weight tensor to form a first pre-processed weight tensor,

perform inter-tile preprocessing of the first pre-processed weight tensor, to form a second pre-processed weight tensor,

perform a first computation cycle on a first row of the second pre-processed weight tensor,

skip a second row of the second pre-processed weight tensor based on the intra-tile preprocessing and the inter-tile preprocessing, and

perform a second computation cycle on a third row of the second pre-processed weight tensor in place of the second row of the second pre-processed weight tensor,

such that the first row of the second pre-processed weight tensor and the third row of the second pre-processed weight tensor are processed in two computation cycles, instead of three computational cycles,

the intra-tile preprocessing comprising causing a first row of a first weight tile of the first weight tensor to be empty by moving a first element of a first weight tile of the first weight tensor by one position, within the first weight tile, in a lookahead direction or in a lookaside direction, and

the inter-tile preprocessing comprising causing the second row of the second pre-processed weight tensor to be empty by moving a second row of a first weight tile of the first pre-processed weight tensor by one position, in a lookahead direction or by one position in a lookaside direction, based on a second row of a second weight tile of the first pre-processed weight tensor being empty.

Assignments (1)

Continuity (2)

References Cited (73)